SPRUJ40F May   2022  – August 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 System Description
      1. 2.1.1 Key Features
        1. 2.1.1.1 Thermal Compliance
        2. 2.1.1.2 Processor
        3. 2.1.1.3 Power Supply
        4. 2.1.1.4 Memory
        5. 2.1.1.5 JTAG/Emulator
        6. 2.1.1.6 Supported Interfaces and Peripherals
        7. 2.1.1.7 Expansion Connectors and Headers to Support Application Specific Add‐On Boards
      2. 2.1.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
      3. 2.1.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
      4. 2.1.4 AM62x SKEVM Interface Mapping
      5. 2.1.5 Power ON/OFF Procedures
        1. 2.1.5.1 Power-On Procedure
        2. 2.1.5.2 Power-Off Procedure
        3. 2.1.5.3 Power Test Points
        4. 2.1.5.4 Power Indication LED
      6. 2.1.6 Peripheral and Major Component Description
        1. 2.1.6.1  Clocking
          1. 2.1.6.1.1 Peripheral Reference Clock
        2. 2.1.6.2  Reset
        3. 2.1.6.3  OLDI Display Interface
        4. 2.1.6.4  CSI
        5. 2.1.6.5  Audio Codec Interface
        6. 2.1.6.6  HDMI Display Interface
        7. 2.1.6.7  JTAG Interface
        8. 2.1.6.8  Test Automation Header
        9. 2.1.6.9  UART Interface
        10. 2.1.6.10 USB Interface
          1. 2.1.6.10.1 USB 2.0 Type A Interface
          2. 2.1.6.10.2 USB 2.0 Type C Interface
        11. 2.1.6.11 Memory Interfaces
          1. 2.1.6.11.1 DDR4 Interface
          2. 2.1.6.11.2 OSPI
          3. 2.1.6.11.3 MMC Interfaces
            1. 2.1.6.11.3.1 MMC0 - eMMC Interface
            2. 2.1.6.11.3.2 MMC1 - Micro SD Interface
            3. 2.1.6.11.3.3 MMC2 - Wi-Fi Interface
          4. 2.1.6.11.4 EEPROM
        12. 2.1.6.12 Ethernet Interface
          1. 2.1.6.12.1 CPSW Ethernet PHY 2 Default Configuration
          2. 2.1.6.12.2 CPSW Ethernet PHY 1 Default Configuration
        13. 2.1.6.13 GPIO Port Expander
        14. 2.1.6.14 GPIO Mapping
        15. 2.1.6.15 Power
          1. 2.1.6.15.1 Power Requirements
          2. 2.1.6.15.2 Power Input
          3. 2.1.6.15.3 Power Supply
          4. 2.1.6.15.4 Power Sequencing
          5. 2.1.6.15.5 AM62x SoC Power
          6. 2.1.6.15.6 Current Monitoring
        16. 2.1.6.16 AM62x SKEVM User Setup and Configuration
          1. 2.1.6.16.1 EVM DIP Switches
          2. 2.1.6.16.2 Boot Modes
          3. 2.1.6.16.3 User Test LEDs
        17. 2.1.6.17 Expansion Headers
          1. 2.1.6.17.1 PRU Connector
          2. 2.1.6.17.2 User Expansion Connector
          3. 2.1.6.17.3 MCU Connector
        18. 2.1.6.18 Interrupt
        19. 2.1.6.19 I2C Address Mapping
  7. 3Additional Information
    1. 3.1 EVM Revisions and Assembly Variants
    2. 3.2 Known Issues and Modifications
      1. 3.2.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
      2. 3.2.2  Issue 2 - J9 and J10 Header Alignment on E1
      3. 3.2.3  Issue 3 - USB Boot descoped on E1
      4. 3.2.4  Issue 4 - OLDI Connector Orientation and Pinout
      5. 3.2.5  Issue 5 - Bluetooth Descoped on E2 EVMs
      6. 3.2.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
      7. 3.2.7  Issue 7 - TEST_POWERDOWN Changes
      8. 3.2.8  Issue 8 - MMC1_SDCD Spurious Interrupts
      9. 3.2.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
      10. 3.2.10 Issue 10 - INA Current Monitor Address Changes
      11. 3.2.11 Issue 11 - Test Automation I2C Buffer Changes
      12. 3.2.12 Issue 12 - ODLI Display Touch Broken
      13. 3.2.13 Issue 13 - Partial IO LPM Not Functional
    3. 3.3 Trademarks
    4.     87
  8. 4Compliance and Certifications
    1. 4.1 EMC, EMI and ESD Compliance
    2.     Regulatory Compliance
  9. 5References
  10. 6Revision History
2.1.6.11.2 OSPI

AM62x SKEVM board has a 512Mbit OSPI memory device from Cypress Part Number S28HS512TGABHM010 which is connected to the OSPI0 interface of the AM62x SoC. The OSPI supports single and double data rates with memory speeds up to 200MBps SDR and 400MBps DDR (200MHz clock speed).

OSPI and QSPI implementation: 0Ω resistors are provided for DATA[7:0], DQS, INT# and CLK signals. Footprints to mount external pull-up resistors are provided on DATA[7:0] to prevent bus floating. The footprint for the OSPI memory also allows the installation of a QSPI memory or an OSPI memory. The 0Ω series resistors provided for pins OSPI_DATA[4:7] is removed if QSPI flash is to be mounted.

Reset: The reset for the OSPI flash is connected to a circuit that ANDs the RESETSTATz from the AM62x with the signal GPIO_OSPI_RSTn from the SoC GPIO. This applies reset for warm and cold reset. A pull-up resistor is provided on GPIO_OSPI_RSTn coming from SoC pin to set the default active state.

Power: The OSPI flash is powered by 1.8V IO supply. The 1.8V supply is provided to the VCC and VCCQ pins of the OSPI flash memory.

The OSPI of the SoC is powered by VDDSHV1 Power group of SoC and is connected to 1.8V IO supply.

SK-AM62, SK-AM62B, SK-AM62B-P1