SPRUJ40F May   2022  – August 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 System Description
      1. 2.1.1 Key Features
        1. 2.1.1.1 Thermal Compliance
        2. 2.1.1.2 Processor
        3. 2.1.1.3 Power Supply
        4. 2.1.1.4 Memory
        5. 2.1.1.5 JTAG/Emulator
        6. 2.1.1.6 Supported Interfaces and Peripherals
        7. 2.1.1.7 Expansion Connectors and Headers to Support Application Specific Add‐On Boards
      2. 2.1.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
      3. 2.1.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
      4. 2.1.4 AM62x SKEVM Interface Mapping
      5. 2.1.5 Power ON/OFF Procedures
        1. 2.1.5.1 Power-On Procedure
        2. 2.1.5.2 Power-Off Procedure
        3. 2.1.5.3 Power Test Points
        4. 2.1.5.4 Power Indication LED
      6. 2.1.6 Peripheral and Major Component Description
        1. 2.1.6.1  Clocking
          1. 2.1.6.1.1 Peripheral Reference Clock
        2. 2.1.6.2  Reset
        3. 2.1.6.3  OLDI Display Interface
        4. 2.1.6.4  CSI
        5. 2.1.6.5  Audio Codec Interface
        6. 2.1.6.6  HDMI Display Interface
        7. 2.1.6.7  JTAG Interface
        8. 2.1.6.8  Test Automation Header
        9. 2.1.6.9  UART Interface
        10. 2.1.6.10 USB Interface
          1. 2.1.6.10.1 USB 2.0 Type A Interface
          2. 2.1.6.10.2 USB 2.0 Type C Interface
        11. 2.1.6.11 Memory Interfaces
          1. 2.1.6.11.1 DDR4 Interface
          2. 2.1.6.11.2 OSPI
          3. 2.1.6.11.3 MMC Interfaces
            1. 2.1.6.11.3.1 MMC0 - eMMC Interface
            2. 2.1.6.11.3.2 MMC1 - Micro SD Interface
            3. 2.1.6.11.3.3 MMC2 - Wi-Fi Interface
          4. 2.1.6.11.4 EEPROM
        12. 2.1.6.12 Ethernet Interface
          1. 2.1.6.12.1 CPSW Ethernet PHY 2 Default Configuration
          2. 2.1.6.12.2 CPSW Ethernet PHY 1 Default Configuration
        13. 2.1.6.13 GPIO Port Expander
        14. 2.1.6.14 GPIO Mapping
        15. 2.1.6.15 Power
          1. 2.1.6.15.1 Power Requirements
          2. 2.1.6.15.2 Power Input
          3. 2.1.6.15.3 Power Supply
          4. 2.1.6.15.4 Power Sequencing
          5. 2.1.6.15.5 AM62x SoC Power
          6. 2.1.6.15.6 Current Monitoring
        16. 2.1.6.16 AM62x SKEVM User Setup and Configuration
          1. 2.1.6.16.1 EVM DIP Switches
          2. 2.1.6.16.2 Boot Modes
          3. 2.1.6.16.3 User Test LEDs
        17. 2.1.6.17 Expansion Headers
          1. 2.1.6.17.1 PRU Connector
          2. 2.1.6.17.2 User Expansion Connector
          3. 2.1.6.17.3 MCU Connector
        18. 2.1.6.18 Interrupt
        19. 2.1.6.19 I2C Address Mapping
  7. 3Additional Information
    1. 3.1 EVM Revisions and Assembly Variants
    2. 3.2 Known Issues and Modifications
      1. 3.2.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
      2. 3.2.2  Issue 2 - J9 and J10 Header Alignment on E1
      3. 3.2.3  Issue 3 - USB Boot descoped on E1
      4. 3.2.4  Issue 4 - OLDI Connector Orientation and Pinout
      5. 3.2.5  Issue 5 - Bluetooth Descoped on E2 EVMs
      6. 3.2.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
      7. 3.2.7  Issue 7 - TEST_POWERDOWN Changes
      8. 3.2.8  Issue 8 - MMC1_SDCD Spurious Interrupts
      9. 3.2.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
      10. 3.2.10 Issue 10 - INA Current Monitor Address Changes
      11. 3.2.11 Issue 11 - Test Automation I2C Buffer Changes
      12. 3.2.12 Issue 12 - ODLI Display Touch Broken
      13. 3.2.13 Issue 13 - Partial IO LPM Not Functional
    3. 3.3 Trademarks
    4.     87
  8. 4Compliance and Certifications
    1. 4.1 EMC, EMI and ESD Compliance
    2.     Regulatory Compliance
  9. 5References
  10. 6Revision History
2.1.6.16.2 Boot Modes

The boot mode for the SK EVM board is defined by two banks of switches SW1 and SW2 or by the I2C buffer connected to the Test automation connector. This allows for AM62x SoC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.

All the bits of switch (SW1 and SW2) have week pull-down resistor and a strong pull-up resistor as shown in below picture.

Note: The OFF setting provides a low logic level (‘0’) and an ON setting provides a high logic level (‘1’).
Note: The boot mode orientation has changed between E1 and future revisions. Please follow board silkscreen.
SK-AM62, SK-AM62B, SK-AM62B-P1 Bootmode Switch Configuration for SD Boot (From E2) Figure 2-19 Bootmode Switch Configuration for SD Boot (From E2)
SK-AM62, SK-AM62B, SK-AM62B-P1 Bootmode Switch Configuration for SD Boot (E1) Figure 2-20 Bootmode Switch Configuration for SD Boot (E1)

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation is provided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the boot mode pins on the AM62x and the output is enabled when the boot mode is needed during a reset cycle. The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the test automation circuit. If the test automation circuit is going to control the boot mode, all the switches are manually set to the OFF position. Power the boot mode buffer with a power supply that is always ON so that the boot mode remains present even if the SoC power is cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode.

The switch map to the boot mode functions is provided in the tables below.

Table 2-20 BOOT-MODE Pin Mapping
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration
  • BOOT-MODE [0:2] – Denote system clock frequency for PLL configuration. By default, this bits are set for 25MHz.

Table 2-21 gives details ON PLL reference clock selection.

Table 2-21 PLL Reference Clock Selection BOOTMODE [2:0]
Bit 2 Bit 1 Bit 0 PLL REF CLK (MHz)
OFF OFF OFF RSVD
OFF OFF ON RSVD
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON RSVD
ON ON OFF RSVD
ON ON ON RSVD
  • BOOT-MODE [3:6] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from. Table 2-22 provides primary boot device selection details.
Table 2-22 Boot Device Selection BOOT-MODE [6:3]
Bit 6 Bit 5 Bit 4 Bit 3 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII1
OFF ON OFF ON Ethernet RMII1
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot
  • BOOT-MODE [10:12] – Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot device failed.

Table 2-23 provides backup boot mode selection details.

Table 2-23 Backup Boot Mode Selection BOOT-MODE [12:10]
Bit 12 Bit 11 Bit 10 Backup Boot Device Selected
OFF OFF OFF None (No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C
  • BOOT-MODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.

Table 2-24 gives primary boot configuration details.

Table 2-24 Primary Boot Mode Configuration [9:7]
SW2.2 (B9) SW2.1 (B8) SW1.8 (B7) Primary Boot Mode
RVSD Read Mode2 0: RSVD (Read mode is taken from Read Mode 1) Read Mode1 0: OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0) Serial NAND
1: SPI/ 1-1-1 Mode (Read mode is taken from Read Mode 2 and Read Mode 1 is ignored) 1: OSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0)
RVSD Iclk 0: Iclock source external Csel 0: Boot Flash is on CS 0 OSPI
1: Iclock source internal (pad loopback) 1: Boot Flash is on CS 1
RVSD Iclk 0: Iclock source external Csel 0: Boot Flash is on CS 0 QSPI
1: Iclock source internal (pad loopback) 1: Boot Flash is on CS 1
RVSD Mode 0: SPI Mode 0 Csel 0: Boot Flash is on CS 0 SPI
1: SPI Mode 3 1: Boot Flash is on CS 1
0 0 Link stat 0: Phy scan used for speed/duplex setup RGMII1
1: RGMII status register used for speed/ duplex setup
CLKOUT 0: 50MHz clock not generated on CLKOUT0 CLK SRC 0: External clock source 0 RMII1
1: 50MHz clock generated on CLKOUT0 1: Internal clock source
Bus reset 0: Hung bus reset try after 1ms RSVD Addr 0: 0x50 I2C0
1: No hung Bus reset attempted 1: 0x51
RSVD RSVD RSVD UART0
1 RSVD Fs/Raw 0: FileSystem Mode MMC/SD Card
1: Raw Mode
RSVD RSVD RSVD eMMC
Core Volt 0: 0.85V Core Voltage Mode 0: DFU(Device) Lane Swap 0: No swapping of DP/DM USB
1: 0.75V Core Voltage 1: MSC(Host) 1: DP/DM is swapped
RSVD RSVD RSVD GPMC NAND
RSVD RSVD RSVD GPMC NOR
RSVD RSVD RSVD RSVD
SFDP 0: SFDP disabled Read Cmd 0: 0x0B Read Command Mode 0: 1S-1S-1S mode at 50MHz xSPI
1: SFDP enabled 1: 0xEE Read Command 1:8D-8D-8D mode at 25MHz
RSVD ARM/ Thumb 0: ARM mode No/Dev 0: Development Boot No-boot/Dev boot
1: Thumb mode 1: No Boot
  • BOOT-MODE [13] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Switch SW2.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
  • BOOT-MODE [14:15] – Reserved.

Table 2-25 provides backup boot configuration options.

Table 2-25 Backup Boot Mode Configuration BOOTMODE [13]
SW2.6 (B13) Backup Boot Mode Defaulted Values for Back up Boot Mode
RSVD None
Mode 0: DFU (Device) USB Core Volt bit = 0 Lane Swap bit = 0
1: MSC(Host)
RSVD RSVD
RSVD UART
Interface 0: RGMII with internal Delay Ethernet Link Stat bit = 0 (If RGMII)
1: RGMII with external clock source ClkOut bit= 0 and Clksrc bit = 1 (If RMII)
1 MMC Mode bit = 0
RSVD SPI Csel bit = 0 Mode = 0
RSVD I2C Addr = 0 Bus Rest = 0