9 DDR Interfaces

The AM62Ax/AM62Dx SoC supports connection to an LPDDR4 device. The DDR signals must be routed at the highest priority, as noted in Table 7-1. For detailed recommendations for DDR routing, see the DDR Routing Guidelines. The images below show the BGA breakout for the DDR interface on the AM62Ax/AM62Dx

The DDR SDRAM memory devices are normally arranged so that the data group balls are closest to the AM62Ax/AM62Dx device. The Package BGA ball map has been carefully planned to place the DDR address and command signals between data byte lanes 0 and 1 and data byte lanes 2 and 3.

Figure 9-1 and Figure 9-2 illustrate how to escape the DDR byte lanes 0 and 1, respectively. Similarly, Figure 9-3 and Figure 9-4 illustrate the escape of DDR byte lanes 2 and 3, respectively. The use of Plated Through Hole (PTH) vias make the routing of these signals between the SoC and SDRAM possible on any layer.

The address, command, and clock signals are routed directly to the memory device.

The top and inner layers are used to escape and route the address and command signals. The traces must be length matched to ensure that the signals arrive at the memory at the same time. Length matching must be from the SoC to memory pin individually, and must include the stub to the memory pad and all via lengths. For detailed recommendations for DDR routing, see the DDR Routing Guidelines.

The escapes of the address and command signals for an LPDDR4 interface on these layers are shown above in Figure 9-5.

Address signals are routed directly from the SoC to the via next to the associated pad for the memory device. This requires that the address signals escape in the correct order. It is required to have the same number of vias for each of the address and command signals. The use of Plated Through Hole (PTH) vias allows the flexibility of routing the address/cmd signals on any layer.