SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1 , TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28378D , TMS320F28379D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

2.1 C29x Architecture Overview

The C29 CPU is an enhanced VLIW (Very Long Instruction Word) architecture with a fully protected pipeline. C29 supports multiple instruction sizes (16, 32, and 48 bits) and a variable instruction packet size which contains instructions that execute in parallel. This is enabled by multiple functional units inside the CPU which can execute concurrently. A total of 64 working registers support the parallel operations in the CPU. In addition to the working registers, the CPU contains multiple status registers which maintain different execution and interrupt context related information. The major features in C29x are specified in Table 2-1.

Table 2-1 C29 Major Feature
Feature Comment
Ease of Use
  • Byte addressable CPU
  • Linear and unified memory map with 4GB address range
  • Fully protected pipeline
  • Deterministic execution without cached memories
Improved Parallelism
  • Execute 1 to 8 instructions in parallel
  • Execute fixed-point, floating point, and addressing operations in parallel
  • Specialized instructions for decision making code and real-time control (example: if-then-else statements, trigonometric and multiphase vector translation operations)
Improved Bus Throughput
  • Capable of fetching up to 128-bit instruction word every cycle
  • Capable of performing 8, 16, 32, 64-bit dual reads and single writes per cycle
  • Improved addressing modes which reduce overhead in accessing memory and peripheral resources
Code Efficiency
  • Supports variable length instruction set (16-bit, 32-bit, and 48-bit)
  • Critical operations are encoded as 16-bit and 32-bit opcodes for improving the code density
  • Rich instruction set optimizes operations in smallest instructions
ASIL-D Safety Capability
  • Support for both Lockstep and split lock modes
  • Integrated ECC logic enables end to end safe interconnect
  • Separate code threads can be fully isolated including stack using SSU
  • Zero CPU overhead switching from one thread to other in HW automatically enabled best real-time performance
Multi-zone Security
  • Run time content protection and IP protection of code
  • Individual passwords for each zone to control access
Enhanced Debug and Trace Capabilities
  • Specialized data logging and code flow trace instructions
  • Trace data capable of being logged in on-chip RAM or exported through serial communication peripherals

Besides from the C29x's feature improvement, there are several new IPs that is used for faster signal chain and safer environment around the CPU.