SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1 , TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28378D , TMS320F28379D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

2.1.3 Real-Time DMA (RTDMA)

The Real-Time (RTDMA) provides a hardware method of transferring data between peripherals and memory without intervention from the CPU in real time. Each of the (2) F29H85x RTDMA modules has ten independent, user-configurable RTDMA channels with an corresponding PIPE vector mapped interrupt to inform the CPU when a RTDMA transfer has either started or completed. All ten channels can be configured at one of four priority levels with one selected channel at a higher priority than the others. Table 2-3 shows the differences between the C28x DMA and the new C29x RTDMA. For more information, see the F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual.

Table 2-3 DMA vs RTDMA
Feature C28x DMA C29x RTDMA
Number of channels

(6) channels with fixed priority level

(10) channels with (4) software configurable priority levels
Burst Mode No Yes (for data transfer through EMIF)
Data Transfer Size 16 and 32-bit data transfers 8, 16, 32, and 64-bit data transfers
Read/Write Interface (1) Read/Write bus – 3 cycles/word without arbitration (2) Independent Read/Write busses – 1 cycle/word without arbitration
Trigger Source System Level Only System Level, Internal channel to channel linking
Safety N/A Integrated Memory Protection Unit configured by system level Safety and Security Unit (SSU)
Security N/A Integrated channel specific secure zones
Transfer Control Linear and Circular Addressing Mode (One Shot, Continuous, Channel Interrupt)
Level/Edge Triggers Triggered by the edge on the trigger inputs
RTDMA Block Diagram Figure 2-4 RTDMA Block Diagram