SPRUJB5 February   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Input
      2. 2.3.2 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbutton
      4. 2.4.4 User Pushbutton And LEDs
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input/Output
      2. 2.5.2 DisplayPort and HDMI
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG and Emulation
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Module
      7. 2.5.7 UARTs for Terminal and Logging
      8. 2.5.8 USB Interfaces
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Camera Interface, 22-Pin Flex
      2. 2.6.2 Camera Interface, 40-Pin Expansion
      3. 2.6.3 CAN-Bus Interface
      4. 2.6.4 DSI Display Interface
      5. 2.6.5 OLDI/LVDS Display Interface
      6. 2.6.6 User Expansion Header
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 I2C Address Mapping
      3. 2.7.3 GPIO Mapping
      4. 2.7.4 I2C GPIO Expander Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Identification EEPROM
      7. 2.7.7 Memory and Storage
      8. 2.7.8 Power Distribution
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 Thermal Compliance
    2. 4.2 EMC, EMI, and ESD Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.6.5 OLDI/LVDS Display Interface

The EVM supports a 40-pin flex (0.5mm pitch) connector [J39] for interfacing with external display modules/panels. The interface provides OLDI/LVDS capable of supporting a single link panel (up to 1920x720p) or dual link panel (up to 3840x1080p). Clock/Control signals, and power (3.3V) are also supported to the panel.

Table 2-15 OLDI/LVDS Display Pin Definition [J39]
Pin # Pin Name Description Dir

1

GND

Ground

2

CH2_LVDS_A3P

LVDS Channel #2 Data Lane 3

Output

3

CH2_LVDS_A3N

LVDS Channel #2 Data Lane 3

Output

4

GND

Ground

5

CH2_LVDS_A2P

LVDS Channel #2 Data Lane 2

Output

6

CH2_LVDS_A2N

LVDS Channel #2 Data Lane 2

Output

7

GND

Ground

8

CH2_LVDS_CLKP

LVDS Channel #2 Clock Lane

Output

9

CH2_LVDS_CLKN

LVDS Channel #2 Clock Lane

Output

10

GND

Ground

11

CH2_LVDS_A1P

LVDS Channel #2 Data Lane 1

Output

12

CH2_LVDS_A1N

LVDS Channel #2 Data Lane 1

Output

13

GND

Ground

14

CH2_LVDS_A0P

LVDS Channel #2 Data Lane 0

Output

15

CH2_LVDS_A0N

LVDS Channel #2 Data Lane 0

Output

16

GND

Ground

17

CH1_LVDS_A3P

LVDS Channel #1 Data Lane 3

Output

18

CH1_LVDS_A3N

LVDS Channel #1 Data Lane 3

Output

19

GND

Ground

20

CH1_LVDS_A2P

LVDS Channel #1 Data Lane 2

Output

21

CH1_LVDS_A2N

LVDS Channel #1 Data Lane 2

Output

22

GND

Ground

23

CH1_LVDS_CLKP

LVDS Channel #1 Clock Lane

Output

24

CH1_LVDS_CLKN

LVDS Channel #1 Clock Lane

Output

25

GND

Ground

26

CH1_LVDS_A1P

LVDS Channel #1 Data Lane 1

Output

27

CH1_LVDS_A1N

LVDS Channel #1 Data Lane 1

Output

28

GND

Ground

29

CH1_LVDS_A0P

LVDS Channel #1 Data Lane 0

Output

30

CH1_LVDS_A0N

LVDS Channel #1 Data Lane 0

Output

31

GND

Ground

32

Interrupt

GPIO, typically used as Interrupt (See GPIO Table)

Bi-Dir

33

Reset

GPIO, typically used as reset (See GPIO Table)

Bi-Dir

34

GND

Ground

35

GND

Ground

36

open/not connected

37

open/not connected

38

I2C_SDA

I2C Data (I2C1)

Bi-Dir

39

I2C_SCL

I2C Clock (I2C1)

Output

40

Power

Power, 3.3V

Output