SPRUJE4D August   2024  – June 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Quick Start Setup
      1. 2.1.1 Configuration 1: Stand-alone Configuration
      2. 2.1.2 Configuration 2: C2000 controlCARD Compatibility Configuration Using HSEC180ADAPEVM
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Design Details
      1. 2.2.1 Power Tree
      2. 2.2.2 Clocking
      3. 2.2.3 Reset
      4. 2.2.4 Board ID EEPROM
    3. 2.3  Power Requirements
    4. 2.4  Configuration Options
      1. 2.4.1 Boot Mode Selection
      2. 2.4.2 ADC Voltage Reference Selection
      3. 2.4.3 MCAN-A Boot Support
      4. 2.4.4 FSI DLT Support
      5. 2.4.5 EtherCAT PHY Clock Selection
    5. 2.5  Header Information
      1. 2.5.1 Baseboard Headers (J1, J2, J3)
      2. 2.5.2 XDS Debug Header (J4)
      3. 2.5.3 DLT Header (J5)
    6. 2.6  Push Buttons
    7. 2.7  User LEDs
    8. 2.8  Debug Information
    9. 2.9  Test Points
    10. 2.10 Best Practices
  8. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
      1. 3.2.1 Install SDK
      2. 3.2.2 Install Additional Software
        1. 3.2.2.1 Install Python
        2. 3.2.2.2 Install OpenSSL
    3. 3.3 Software Development
    4. 3.4 Developing an Application
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Usage Note Matrix
      2. 5.1.2 Advisories Matrix
      3. 5.1.3 Usage Notes
        1. 5.1.3.1 Parallel I/O Boot Can Cause Watchdog Timer Timeout if No Host Is Connected to EVM
        2. 5.1.3.2 Device GPIOs Dedicated to PMIC SPI Bus Should Be Used for SPI Function If Used On Baseboard
      4. 5.1.4 Advisories
        1. 5.1.4.1  MCU Flash Is Not Supported, All Code Must Execute From RAM
        2. 5.1.4.2  Incorrect Package Marking on MCU Package
        3. 5.1.4.3  Internal Oscillator (INTOSC2) on MCU Defaults to 6MHz
        4. 5.1.4.4  By Default, GPIO4 Configured as ERRORSTS by ROM Code and Driven High
        5. 5.1.4.5  MCU Fault State Possible When On-Board 25MHz Clock is Enabled
        6. 5.1.4.6  25MHz X1 Clock Is Disabled, INTOSC Must Be Used as MCU Clock Source and EtherCAT Is Not Supported
        7. 5.1.4.7  PMIC Monitoring of MCU Reset Signal (XRSN) Is Disabled
        8. 5.1.4.8  ADC VREFHIAB and VREFHICDE Incorrectly Shorted Together When S3 and S4 Are Both Set to Internal VREF Mode
        9. 5.1.4.9  Incorrect Voltage on VREFHIAB and VREFHICDE Pins When External VREF Mode Is Selected
        10. 5.1.4.10 MCU Reset Signal (XRSN) Can Remain Asserted on Power-On
        11. 5.1.4.11 FSI Signals on the Data Logging and Trace Connector (J5) May Interfere With Some Advanced Debuggers
    2. 5.2 Trademarks
  11. 6References
  12. 7Revision History

2.8 Debug Information

This section describes frequently asked questions about the F29H85X-SOM-EVM.

  1. Can other programming and debug tools (such as an XDS200 debug probe) be used with the controlSOM?
    1. Yes, when the controlSOM is paired with the HSEC180ADAPEVM adapter board and the TMDSHSECDOCK baseboard docking station, a debug probe such as the XDS200 can be used. Also, an XDS560v2 debug probe with a MIPI-60 connector can connect directly to the DLT header (J5) on the controlSOM.
  2. Why can't I connect to the controlSOM in Code Composer Studio?
    1. Make sure there is power on the controlSOM by verifying that LED1 (5.0V input) and LED2 (3.3V output) are on.
    2. Check that power is being delivered to the F29H85x device by probing TP1 (VDD, 1.25V), TP2 (VDDIO, 3.3V), and TP14 (VDDA, 3.3V).
    3. Check that the F29H85x device is out of reset by probing TP15. This test point must read close to 3.3V when the device is out of reset.
    4. If using Configuration 2 or Configuration 3, check that the XDS110ISO-EVM is configured for full JTAG mode. Switch S1 on the XDS110ISO-EVM must be set to the JTAG setting.
    5. Make sure that the target configuration is set up to use full JTAG mode (see Figure 2-14). Open the Target Configuration file (.ccxml) in Code Composer Studio. Click on the Advanced tab and select "JTAG (1149.1), SWD and cJTAG are disabled" from the "JTAG/SWD/cJTAG Mode" drop-down. Alternatively, a working target configuration file is included in all the F29 SDK examples. This file can be used without modifications.
    F29H85X-SOM-EVM Target Configuration Advanced Options Figure 2-14 Target Configuration Advanced Options
  3. Why does the F29H85X-SDK SPI example fail in external loopback mode?
    • If using the XDS110ISO-EVM, check that the DAC SPI POCI pin is disabled by switching the POCI S2 switch on the XDS110ISO-EVM to the OFF position.
    • The F29H85X-SDK SPI example documents the external connections required for the example to work. Review the F29H85x controlSOM pinout map to make sure that the external connections are implemented correctly.
  4. Why am I unable to send or receive data from the XDS110ISO-EVM through the virtual COM port?