SPRUJE4D August   2024  – June 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Quick Start Setup
      1. 2.1.1 Configuration 1: Stand-alone Configuration
      2. 2.1.2 Configuration 2: C2000 controlCARD Compatibility Configuration Using HSEC180ADAPEVM
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Design Details
      1. 2.2.1 Power Tree
      2. 2.2.2 Clocking
      3. 2.2.3 Reset
      4. 2.2.4 Board ID EEPROM
    3. 2.3  Power Requirements
    4. 2.4  Configuration Options
      1. 2.4.1 Boot Mode Selection
      2. 2.4.2 ADC Voltage Reference Selection
      3. 2.4.3 MCAN-A Boot Support
      4. 2.4.4 FSI DLT Support
      5. 2.4.5 EtherCAT PHY Clock Selection
    5. 2.5  Header Information
      1. 2.5.1 Baseboard Headers (J1, J2, J3)
      2. 2.5.2 XDS Debug Header (J4)
      3. 2.5.3 DLT Header (J5)
    6. 2.6  Push Buttons
    7. 2.7  User LEDs
    8. 2.8  Debug Information
    9. 2.9  Test Points
    10. 2.10 Best Practices
  8. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
      1. 3.2.1 Install SDK
      2. 3.2.2 Install Additional Software
        1. 3.2.2.1 Install Python
        2. 3.2.2.2 Install OpenSSL
    3. 3.3 Software Development
    4. 3.4 Developing an Application
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Usage Note Matrix
      2. 5.1.2 Advisories Matrix
      3. 5.1.3 Usage Notes
        1. 5.1.3.1 Parallel I/O Boot Can Cause Watchdog Timer Timeout if No Host Is Connected to EVM
        2. 5.1.3.2 Device GPIOs Dedicated to PMIC SPI Bus Should Be Used for SPI Function If Used On Baseboard
      4. 5.1.4 Advisories
        1. 5.1.4.1  MCU Flash Is Not Supported, All Code Must Execute From RAM
        2. 5.1.4.2  Incorrect Package Marking on MCU Package
        3. 5.1.4.3  Internal Oscillator (INTOSC2) on MCU Defaults to 6MHz
        4. 5.1.4.4  By Default, GPIO4 Configured as ERRORSTS by ROM Code and Driven High
        5. 5.1.4.5  MCU Fault State Possible When On-Board 25MHz Clock is Enabled
        6. 5.1.4.6  25MHz X1 Clock Is Disabled, INTOSC Must Be Used as MCU Clock Source and EtherCAT Is Not Supported
        7. 5.1.4.7  PMIC Monitoring of MCU Reset Signal (XRSN) Is Disabled
        8. 5.1.4.8  ADC VREFHIAB and VREFHICDE Incorrectly Shorted Together When S3 and S4 Are Both Set to Internal VREF Mode
        9. 5.1.4.9  Incorrect Voltage on VREFHIAB and VREFHICDE Pins When External VREF Mode Is Selected
        10. 5.1.4.10 MCU Reset Signal (XRSN) Can Remain Asserted on Power-On
        11. 5.1.4.11 FSI Signals on the Data Logging and Trace Connector (J5) May Interfere With Some Advanced Debuggers
    2. 5.2 Trademarks
  11. 6References
  12. 7Revision History

2.4.4 FSI DLT Support

An optional resistor configuration is included on the F29H85x controlSOM to enable use of multiple FSI pins for data logging through the data, logging, and trace (DLT) header (J5). Table 2-7 lists all the FSI pins that can be connected to the DLT header. By default, these FSI pins are connected to the J1/J3 high-density connectors for baseboard use; the FSI pins are not connected to the DLT header. To connect these FSI pins to the DLT header, follow the instructions on Table 2-8.

F29H85X-SOM-EVM FSI DLT Selection Resistors Figure 2-11 FSI DLT Selection Resistors
F29H85X-SOM-EVM FSI DLT Selection Resistor Locations (Top) Figure 2-12 FSI DLT Selection Resistor Locations (Top)
F29H85X-SOM-EVM FSI DLT Selection Resistor Locations (Bottom) Figure 2-13 FSI DLT Selection Resistor Locations (Bottom)
Table 2-7 FSI Pins Used for DLT Support
GPIO Function
GPIO51 FSITXA_CLK
GPIO49 FSITXA_D0
GPIO50 FSITXA_D1
GPIO8 FSITXB_CLK
GPIO6 FSITXB_D0
GPIO7 FSITXB_D1
GPIO16 FSIRXC_CLK
GPIO76 FSIRXC_D0
Table 2-8 FSI GPIO Baseboard/DLT Header Connection
Mode Resistor Configuration
FSI pins connected to J1/J3 Baseboard Headers (default) Populate all 0-ohm resistors on R52, R86, R93, R55, R88, R94, R81, and R89.

Remove all resistors on R82, R90, R95, R83, R91, R96, R84, and R92.
FSI GPIOs connected to DLT Header Remove all resistors on R52, R86, R93, R55, R88, R94, R81, and R89.

Populate all 0-ohm resistors on R82, R90, R95, R83, R91, R96, R84, and R92.