STDA041 October   2026 OPA690

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Design Summary
  5. 2Theory of Operation
    1. 2.1 Circuit Overview
    2. 2.2 Closed-loop Operation
    3. 2.3 FET Operation Region
  6. 3Design Procedure
    1. 3.1 Choosing FET
      1. 3.1.1 Ciss
      2. 3.1.2 Compliance Voltage Range
      3. 3.1.3 Safe Operating Area (SOA)
    2. 3.2 Rsense Selection
      1. 3.2.1 Effect of ESL
    3. 3.3 Opamp Selection
      1. 3.3.1 Bandwidth
      2. 3.3.2 Slew Rate
      3. 3.3.3 Opamp Output Current
  7. 4Design Based Component Selection
    1. 4.1 Design for Trise = 100ns
      1. 4.1.1 FET Selection
      2. 4.1.2 Rsense Selection
      3. 4.1.3 Opamp Selection
        1. 4.1.3.1 Bandwidth
        2. 4.1.3.2 Slew Rate
        3. 4.1.3.3 Output Current
    2. 4.2 Architecture Selection (Quick Reference)
  8. 5Circuit Architecture Selection
    1. 5.1 Single Feedback Method
    2. 5.2 Dual Feedback Method
    3. 5.3 Enhanced Dual Feedback Method
  9. 6Results
  10. 7Related Documentation

3.2.1 Effect of ESL

The parasitic ESL of the sense resistor forms an L/R low-pass filter with Rsense, since the feedback voltage VFB is sensed directly across Rsense. During a current transient, the ESL opposes the rapid change in current, and the feedback voltage only settles to the true value after a time-constant of τ = ESL+ LSource / Rsense, giving a rise-time of approximately:

Equation 5.   T r i s e =   2 τ   =   2   × (   E S L   +   L s o u r c e ) R s e n s e  

This creates a fundamental conflict, reducing Rsense minimizes power dissipation but directly increases the L/R time constant and slows down the feedback response, resulting in a rise-time beyond the required specification. Therefore, Rsense cannot be reduced arbitrarily, and the rise-time constraint sets a lower limit for Rsense.