STDA041 October   2026 OPA690

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Design Summary
  5. 2Theory of Operation
    1. 2.1 Circuit Overview
    2. 2.2 Closed-loop Operation
    3. 2.3 FET Operation Region
  6. 3Design Procedure
    1. 3.1 Choosing FET
      1. 3.1.1 Ciss
      2. 3.1.2 Compliance Voltage Range
      3. 3.1.3 Safe Operating Area (SOA)
    2. 3.2 Rsense Selection
      1. 3.2.1 Effect of ESL
    3. 3.3 Opamp Selection
      1. 3.3.1 Bandwidth
      2. 3.3.2 Slew Rate
      3. 3.3.3 Opamp Output Current
  7. 4Design Based Component Selection
    1. 4.1 Design for Trise = 100ns
      1. 4.1.1 FET Selection
      2. 4.1.2 Rsense Selection
      3. 4.1.3 Opamp Selection
        1. 4.1.3.1 Bandwidth
        2. 4.1.3.2 Slew Rate
        3. 4.1.3.3 Output Current
    2. 4.2 Architecture Selection (Quick Reference)
  8. 5Circuit Architecture Selection
    1. 5.1 Single Feedback Method
    2. 5.2 Dual Feedback Method
    3. 5.3 Enhanced Dual Feedback Method
  9. 6Results
  10. 7Related Documentation

3.1.2 Compliance Voltage Range

To verify that the FET stays in saturation, the designer must consult two key curves from the datasheet. First, the ID versus VGS transfer characteristic determines the maximum gate-to-source voltage (VGS, maximum) required to drive the full output current. This value is the VGS at which ID equals the target output current. Second, the ID versus VDS output characteristics are examined at that specific VGS maximum to identify the knee-point voltage, which is the minimum VDS at which ID saturates and becomes independent of VDS. This knee-point voltage represents the minimum headroom the FET requires to stay in saturation.

The minimum compliance voltage of the application must exceed the knee-point VDS identified above by a sufficient margin. If the minimum compliance voltage is too close to or below the knee-point, the FET enters the ohmic region under worst-case conditions, and a different device with a lower Vth or a sharper saturation knee must be selected.

OPA690 Typical Output CharacteristicsFigure 3-1 Typical Output Characteristics
OPA690 Typical Transfer CharacteristicsFigure 3-2 Typical Transfer Characteristics

As a worked example, the typical output and transfer characteristics of the FET, IQE013N04LM6CGSC are shown in Figure 3-1 and Figure 3-2. Figure 3-1 shows the drain current variation with drain-to-source voltage for different gate-to-source voltages, where the drain current increases rapidly before entering the saturation region. Figure 3-2 shows the transfer characteristics at 25°C and 175°C, indicating the variation of drain current with gate-to-source voltage and the effect of temperature on the device current. These characteristics are useful for determining the operating region and providing sufficient voltage margin during FET operation.