STDA041 October   2026 OPA690

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Design Summary
  5. 2Theory of Operation
    1. 2.1 Circuit Overview
    2. 2.2 Closed-loop Operation
    3. 2.3 FET Operation Region
  6. 3Design Procedure
    1. 3.1 Choosing FET
      1. 3.1.1 Ciss
      2. 3.1.2 Compliance Voltage Range
      3. 3.1.3 Safe Operating Area (SOA)
    2. 3.2 Rsense Selection
      1. 3.2.1 Effect of ESL
    3. 3.3 Opamp Selection
      1. 3.3.1 Bandwidth
      2. 3.3.2 Slew Rate
      3. 3.3.3 Opamp Output Current
  7. 4Design Based Component Selection
    1. 4.1 Design for Trise = 100ns
      1. 4.1.1 FET Selection
      2. 4.1.2 Rsense Selection
      3. 4.1.3 Opamp Selection
        1. 4.1.3.1 Bandwidth
        2. 4.1.3.2 Slew Rate
        3. 4.1.3.3 Output Current
    2. 4.2 Architecture Selection (Quick Reference)
  8. 5Circuit Architecture Selection
    1. 5.1 Single Feedback Method
    2. 5.2 Dual Feedback Method
    3. 5.3 Enhanced Dual Feedback Method
  9. 6Results
  10. 7Related Documentation

4.1.1 FET Selection

Applying the same bandwidth-to-rise time relationship established earlier:

B W r e q u i r r e d =   0.35 T r i s e =   0.35 100 n s =   3.5 M H z

The Rdamp–Ceff low-pass filter pole must lie above this bandwidth:

f p o l e =   1 2 π   ×   R d a m p × C e f f ≥   3.5 M H z

solving for Ceff: Ceff ≤ 9.09nF

So the FET's effective input capacitance must be below 9.09nF for this design.

  1. Input capacitance, Ciss

    We are supposed to look into the FETs with Ciss less than 9.1nF, and by also considering the gm effect of capacitance variation we must chose FET’s with Ciss less than 7.6nF.

    From the Ciss criteria and our desired current specification we opted for IQE013N04LM6CGSC (Ciss= 3.3nF).
  2. Compliance voltage

    From the IQE013N04LM6CGSC datasheet the maximum current requirement drives VGS(max) to 3V. Mapping this requirement with the output characteristics of the FET shows that the FET operates in saturation for voltages above 0.5-0.6V. For our minimum compliance specification of 0.4V, the FET operates around the transition region from ohmic to saturation. Ramping up the compliance voltage to 0.7-0.8V keeps the FET in saturation.

  3. SOA

    This design targets 150A output current at a minimum compliance voltage of 0.5V, with a pulse duration of 100µs. Reading the SOA curve at VDS = 0.4V along the 100µs boundary, the IQE013N04LM6CGSC supports well over 100A operating point. The device operates entirely within the safe region with substantial margin, confirming SOA does not restrict the design.