STDA041 October   2026 OPA690

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Design Summary
  5. 2Theory of Operation
    1. 2.1 Circuit Overview
    2. 2.2 Closed-loop Operation
    3. 2.3 FET Operation Region
  6. 3Design Procedure
    1. 3.1 Choosing FET
      1. 3.1.1 Ciss
      2. 3.1.2 Compliance Voltage Range
      3. 3.1.3 Safe Operating Area (SOA)
    2. 3.2 Rsense Selection
      1. 3.2.1 Effect of ESL
    3. 3.3 Opamp Selection
      1. 3.3.1 Bandwidth
      2. 3.3.2 Slew Rate
      3. 3.3.3 Opamp Output Current
  7. 4Design Based Component Selection
    1. 4.1 Design for Trise = 100ns
      1. 4.1.1 FET Selection
      2. 4.1.2 Rsense Selection
      3. 4.1.3 Opamp Selection
        1. 4.1.3.1 Bandwidth
        2. 4.1.3.2 Slew Rate
        3. 4.1.3.3 Output Current
    2. 4.2 Architecture Selection (Quick Reference)
  8. 5Circuit Architecture Selection
    1. 5.1 Single Feedback Method
    2. 5.2 Dual Feedback Method
    3. 5.3 Enhanced Dual Feedback Method
  9. 6Results
  10. 7Related Documentation

3.1 Choosing FET

The design process initiates with the selection of the FET, which is governed by three primary performance metrics:

  1. Input Capacitance, Ciss
  2. Compliance Voltage Range
  3. Safe Operating Area, SOA