TIDUDA6A December   2017  – January 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

7.2 SNR Measurement Test

The steps for testing the SNR measurement for a 2.7-GHz sample rate are as follows:

  1. Emulate the hardware setup as shown in Figure 7-1, then provide the input signal to the J12 SMA connector of channel 1 of the TIDA-01022 design through a variable band-pass filter.
  2. Connect the high-speed USB3.0 and USB2.0 cables to the capture PC.
  3. Provide a 12-V, 4-A DC supply to the power connector of J55 and provide a 5-V supply to the TSW14J56 capture card.

To measure the signal chain SNR, configure the following using the HSDC TID GUI:

  1. Use the J32 connector to program the LMK61E2 device at 33.75 MHz using the USB2ANY programmer associated with the LMK61E2 Oscillator Programming Tool. Set the device address as 0x5A before programming.
  2. Program the LMK04828 in 0-delay PLL mode at a 33.75-MHz SYSREF frequency to provide the SYSREFREQ and SYNC signals along with this 33.75-MHz OSCout as a reference to the LMX2594.
  3. The LMK04828 also generates the FPGA reference at 270 MHz, the FPGA core clock at 270 MHz, and the FPGA SYSREF at 33.75 MHz for the FPGA capture card.
  4. Program the LMX2594_A for a 2.7-GHz DEVCLK and SYSREF at 33.75 MHz.
  5. Configure ADC12DJ3200 JMODE-2 (dual-channel mode) by loading the configuration file in the low-level page.

Establish the JESD204B link using HSDC Pro GUI:

  1. After powering the TSW14J56, establish a connection with the dual-channel mode (JMODE2).
  2. Provide the data rate sampling frequency of the ADC output data and the ADC input target frequency.
  3. Afer establishing the JESD204B connection, feed the input signal to J12 from the signal generator.
  4. Capture the spectrum and note the SNR performance.
  5. Repeat the test with different inputs and sampling frequencies and tabulate the results.
Note:

The TIDA-01022 design folder contains the necessary configuration files for generating the different sample rates: 2.7 GHz and 3 GHz.