TIDUDT4A May   2018  – November 2021 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Power Rails Requirements of the System
      2. 2.2.2 Power Sequencing Requirements of the System
      3. 2.2.3 Uncontrolled Power Off
      4. 2.2.4 12-V Input Voltage Rail
    3. 2.3 Highlighted Products
      1. 2.3.1 TLV62568/9
      2. 2.3.2 LM3881
      3. 2.3.3 TLV803
      4. 2.3.4 AM335x
      5. 2.3.5 WL1837MOD
    4. 2.4 System Design Theory
      1. 2.4.1 Power Tree Architecture
      2. 2.4.2 Power Sequencing Solution
        1. 2.4.2.1 Design Steps for DC-DCs
        2. 2.4.2.2 Design Steps for the Sequencer
        3. 2.4.2.3 Design Steps for the Supervisor
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Connector Configuration of TIDA-01568
        2. 3.1.1.2 Procedure for Board Bring-up and Testing
      2. 3.1.2 Software
        1. 3.1.2.1 Description of Environment Implementation
        2. 3.1.2.2 How to Customize the Processor SDK for This Reference Design
      3. 3.1.3 Software Bring-up Tips
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Power-Up and Power-Down Sequence Test
        2. 3.2.2.2 Typical Characteristics of DC-DCs
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 PCB Layout Guidelines
      2. 4.3.2 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History

3.2.2.1 Power-Up and Power-Down Sequence Test

The following waveforms show the power-up and power-down sequence provided by this power solution that meet the requirements of the AM335x. The test environment includes the following:

  1. The input capacitor is 220 µF.
  2. The status of the board is: Linux running with Wi-Fi enabled.
  3. The style of the power down directly removes the DC power through the switch.

Figure 3-4 shows the power sequences of the input voltage rail and 1.8-V, 3.3-V, and 1.35-V rails.

GUID-91C8DB88-0F7C-43DD-8389-CACF895BE02F-low.gifFigure 3-4 Power Sequence for 5-Vin,1.8-V, 3.3-V, and 1.35-V Rails

For the power-up sequencing, the 1.8-V, 1.35-V, and 3.3-V rails power turn on sequentially after the input voltage rail turns on. For the power-down sequencing, the 3.3-V, 1.35-V, and 1.8-V rails turn off sequentially in the precise reverse order after the input voltage rail turns off. The delay time between the different power rails is approximately 10 ms, which can be adjusted by changing the external capacitor of the LM3881MM.

Figure 3-5 shows the power sequences of the 3.3-V, 1.8-V, 1.35-V, and 1.1-V rails.

GUID-79829383-AEE3-4DFC-9E19-E503F1A2A47C-low.gifFigure 3-5 Power Sequence for 3.3-V, 1.8-V, 1.35-V, and 1.1-V Rails

For the power-up sequencing, the 1.8-V, 1.35-V, and 3.3-V rails power turn on sequentially after the input voltage rail turns on. For the power-down sequencing, the 3.3-V, 1.35-V, and 1.8-V rails turn off sequentially in the precise reverse order after the input voltage rail turns off. The difference between VDDS and VDDSHVx[1-6] during the entire power down sequence is < 2 V.

Figure 3-6 shows the power sequences of the 5-Vin, 1.8-V, 3.3-V, and PWRONRSTn rails.

GUID-6D0C4D01-CB24-4D91-BB92-0600010C39BB-low.gifFigure 3-6 Power Sequence for 5-Vin, 1.8-V, 3.3-V, and PWRONRSTn Rails

For the power-up sequencing, the 1.8-V, 3.3-V, and PWRONRSTn rails turn on sequentially after the input voltage rail turns on, and the PWRONRSTn rail turns on after all the other rails are ON. For the power-down sequencing, the PWRONRSTn rail ramps down first before all other rails turn off, and the other rails ramp down sequentially. The delay time between PWRONRSTn and input voltage rail is 200 ms, which depends on the fixed delay time of the supervisor for the TLV803.

Figure 3-7 shows the power sequences of the 1.8-V, 3.3-V, 1.1-V, and 1.325-V rails.

GUID-77782325-3AE7-4DCB-AF34-5254F58BC9F1-low.gifFigure 3-7 Power Sequence for 1.8-V, 3.3-V, 1.1-V, and 1.325-V Rails

For the power-up sequencing, the 1.8-V, 3.3-V, 1.1-V, and 1.325-V rails turn on sequentially, and the 1.325-V and 1.1-V rails ramp up at the same time. For the power-down sequencing, the 1.8-V, 3.3-V, 1.1-V, and 1.325-V rails ramp down sequentially, and the 1.325-V and 1.1-V rails ramp down at the same time.