Product details


Arm MHz (Max.) 800 Serial I/O CAN, I2C, SPI, UART, USB Co-processor(s) PRU-ICSS Graphics acceleration 1 3D Ethernet MAC 2-Port 10/100 PRU EMAC, 2-Port 1Gb Switch Industrial protocols EtherNet/IP, PROFIBUS, PROFINET RT/IRT, SERCOS III Security enabler Cryptographic acceleration Operating temperature range (C) -40 to 105 Display type 1 LCD DRAM DDR2, DDR3, DDR3L, LPDDR Arm CPU 1 Arm Cortex-A8 Rating HiRel Enhanced Product USB 2.0 2 open-in-new Find other AM335x Arm Cortex-A8 processors

Package | Pins | Size

NFBGA (GCZ) 324 225 mm² 15 x 15 open-in-new Find other AM335x Arm Cortex-A8 processors


  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch

All trademarks are the property of their respective owners.

open-in-new Find other AM335x Arm Cortex-A8 processors


The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

open-in-new Find other AM335x Arm Cortex-A8 processors

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet AM3358-EP Sitara™ Processor datasheet (Rev. B) Apr. 18, 2019
* Errata AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) Jan. 03, 2017
* User guides AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) Dec. 13, 2019
* Radiation & Reliability reports AM3358BGCZA80EP Reliability Report Dec. 17, 2015
White papers EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) Jul. 28, 2020
Application notes AM335x Schematic Checklist (Rev. A) Dec. 19, 2019
Technical articles Designing smarter remote terminal units for microgrids Oct. 02, 2019
Application notes Programmable Logic Controllers — Security Threats and Solutions Sep. 13, 2019
More literature Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) Jul. 30, 2019
White papers Power optimization techniques for energy-efficient systems (Rev. A) Jun. 28, 2019
Technical articles Security versus functional safety: a view from the Processor Software Development Kit May 31, 2019
White papers Sitara Processor Security (Rev. D) May 09, 2019
Application notes AM335x Hardware Design Guide May 03, 2019
User guides Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 Apr. 11, 2019
Application notes Common EOS pitfalls in board design Feb. 13, 2019
Application notes McASP Design Guide - Tips, Tricks, and Practical Examples Jan. 10, 2019
Application notes PRU Read Latencies (Rev. A) Dec. 21, 2018
White papers Ensuring real-time predictability (Rev. B) Dec. 04, 2018
Application notes PRU-ICSS EtherCAT Slave Troubleshooting Guide Nov. 07, 2018
Application notes PRU-ICSS / PRU_ICSSG Migration Guide Nov. 05, 2018
Application notes High-Speed Interface Layout Guidelines (Rev. H) Oct. 11, 2018
Technical articles Simplified software development through the Processor SDK and tools Oct. 02, 2018
White papers Time sensitive networking for industrial automation (Rev. A) Oct. 02, 2018
User guides How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS Sep. 24, 2018
Technical articles Processor SDK: one for all and all for one Jun. 27, 2018
Application notes Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) Mar. 28, 2018
User guides Powering the AM335x With the TPS650250 (Rev. B) Mar. 14, 2018
White papers Data concentrators: The core of energy and data management (Rev. A) Feb. 21, 2018
White papers POWERLINK on TI Sitara Processors (Rev. A) Jan. 10, 2018
More literature TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) Dec. 19, 2017
Application notes Ethernet PHY Configuration Using MDIO for Industrial Applications Dec. 11, 2017
User guides TPS65910Ax User's Guide for AM335x Processors (Rev. F) Dec. 08, 2017
Application notes AM335x Reliability Considerations in PLC Applications (Rev. A) Apr. 27, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
White papers Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) Aug. 11, 2016
VID AM3358-EP VID V6215602 Jun. 21, 2016
White papers Building automation for enhanced energy and operational efficiency (Rev. A) Oct. 26, 2015
White papers Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) Mar. 03, 2015
User guides G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide Nov. 13, 2014
User guides Powering the AM335x with the TPS65217x . (Rev. I) Sep. 06, 2014
White papers Mainline Linux™ ensures stability and innovation Mar. 27, 2014
White papers Linaro Speeds Development in TI Linux SDKs Aug. 27, 2013
White papers The Yocto Project:Changing the way embedded Linux software solutions are develop Mar. 14, 2013
White papers Smart thermostats are a cool addition to the connected home Sep. 27, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The Element14 development kit for the TI SimpleLink™ Sub-1 GHz Sensor to Cloud Linux Gateway provides an out of the box, end-to-end solution enabling an easy cloud connection for sending and receiving long range sensor data while maintaining a robust link. The kit contains all of the components (...)

  • Large network with long range mode and cloud connectivity
  • Suitable for industrial settings such as building control and asset tracking
  • Provides a complete Sub-1 GHz networking solution with built-in frequency hopping for added robustness and FCC compliance
  • Faster time to market with a complete end to (...)

Software development

XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Design tools & simulation

Pin mux tool
PINMUXTOOL The PinMux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or (...)

Reference designs

Acontis EtherCAT Master Stack Reference Design
TIDEP0043 The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performance TI Sitara MPUs,  it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT (...)
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