Product details

Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 800 Co-processor(s) PRU-ICSS CPU 32-bit Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, Profibus, Profinet, ICSS Ethernet MAC 2-Port 10/100 PRU EMAC, 2-Port 1Gb switch Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (C) -40 to 105
Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 800 Co-processor(s) PRU-ICSS CPU 32-bit Graphics acceleration 1 3D Display type 1 LCD Protocols Ethernet, Profibus, Profinet, ICSS Ethernet MAC 2-Port 10/100 PRU EMAC, 2-Port 1Gb switch Operating system Linux, RTOS Rating HiRel Enhanced Product Operating temperature range (C) -40 to 105
NFBGA (GCZ) 324 225 mm² 15 x 15
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch
  • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32‑bit RISC processor
    • NEON™ SIMD coprocessor
    • 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
    • 256KB of L2 cache with error correcting code (ECC)
    • 176KB of on-chip boot ROM
    • 64KB of dedicated RAM
    • Emulation and debug - JTAG
    • Interrupt controller (up to 128 interrupt requests)
  • On-chip memory (shared L3 RAM)
    • 64KB of general-purpose on-chip memory controller (OCMC) RAM
    • Accessible to all masters
    • Supports retention for fast wakeup
  • External memory interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
      • mDDR: 200-MHz clock (400-MHz data rate)
      • DDR2: 266-MHz clock (532-MHz data rate)
      • DDR3: 400-MHz clock (800-MHz data rate)
      • DDR3L: 400-MHz clock (800-MHz data rate)
      • 16-bit data bus
      • 1GB of total addressable space
      • Supports one x16 or two x8 memory device configurations
    • General-purpose memory controller (GPMC)
      • Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH code to support 4-, 8-, or 16-bit ECC
      • Uses hamming code to support 1-bit ECC
    • Error locator module (ELM)
      • Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
  • Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
    • Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
    • Two programmable real-time units (PRUs)
      • 32-bit load/store RISC processor capable of running at 200 MHz
      • 8KB of instruction RAM with single-error detection (parity)
      • 8KB of data RAM with single-error detection (parity)
      • Single-cycle 32-bit multiplier with 64-bit accumulator
      • Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
    • 12KB of shared RAM with single-error detection (parity)
    • Three 120-byte register banks accessible by each PRU
    • Interrupt controller (INTC) for handling system input events
    • Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
    • Peripherals inside the PRU-ICSS:
      • One UART port with flow control pins, supports up to 12 Mbps
      • One enhanced capture (eCAP) module
      • Two MII Ethernet ports that support industrial ethernet
      • One MDIO port
  • Power, reset, and clock management (PRCM) module
    • Controls the entry and exit of stand-by and deep-sleep modes
    • Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
    • Clocks
      • Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
      • Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
      • Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
    • Power
      • Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
      • Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
      • Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
      • Dynamic voltage frequency scaling (DVFS)
  • Real-time clock (RTC)
    • Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
    • Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
    • Independent power-on-reset (RTC_PWRONRSTn) input
    • Dedicated input pin (EXT_WAKEUP) for external wake events
    • Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
    • Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
  • Peripherals
    • Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
    • Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
      • Integrated switch
      • Each MAC supports MII, RMII, RGMII, and MDIO interfaces
      • Ethernet MACs and switch can operate independent of other functions
      • IEEE 1588v2 precision time protocol (PTP)
    • Up to two controller-area network (CAN) ports
      • Supports CAN version 2 parts A and B
    • Up to two multichannel audio serial ports (McASPs)
      • Transmit and receive clocks up to 50 MHz
      • Up to four serial data pins per McASP port with independent TX and RX clocks
      • Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
      • Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
      • FIFO buffers for transmit and receive (256 bytes)
    • Up to six UARTs
      • All UARTs support IrDA and CIR modes
      • All UARTs support RTS and CTS flow control
      • UART1 supports full modem control
    • Up to two master and slave McSPI serial interfaces
      • Up to two chip selects
      • Up to 48 MHz
    • Up to three MMC, SD, SDIO ports
      • 1-, 4-, and 8-bit MMC, SD, SDIO modes
      • MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
      • Up to 48-MHz data transfer rate
      • Supports card detect and write protect
      • Complies with MMC4.3, SD, SDIO 2.0 specifications
    • Up to three I2C master and slave interfaces
      • Standard mode (up to 100 kHz)
      • Fast mode (up to 400 kHz)
    • Up to four banks of general-purpose I/O (GPIO) pins
      • 32 GPIO pins per bank (multiplexed with other functional pins)
      • GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
    • Up to three external DMA event inputs that can also be used as interrupt inputs
    • Eight 32-bit general-purpose timers
      • DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
      • DMTIMER4–DMTIMER7 are pinned out
    • One watchdog timer
    • SGX530 3D graphics engine
      • Tile-based architecture delivering up to 20 million polygons per second
      • Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
      • Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-grained task switching, load balancing, and power management
      • Advanced geometry DMA-driven operation for minimum CPU interaction
      • Programmable high-quality image anti-aliasing
      • Fully virtualized memory addressing for OS operation in a unified memory architecture
    • LCD controller
      • Up to 24-bit data output; 8 bits per pixel (RGB)
      • Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
      • Integrated LCD interface display driver (LIDD) controller
      • Integrated raster controller
      • Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
      • 512-word deep internal FIFO
      • Supported display types:
        • Character displays - uses LIDD controller to program these displays
        • Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
        • Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
    • 12-bit successive approximation register (SAR) ADC
      • 200K samples per second
      • Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
      • Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
    • Up to three 32-bit eCAP modules
      • Configurable as three capture inputs or three auxiliary PWM outputs
    • Up to three enhanced high-resolution PWM modules (eHRPWMs)
      • Dedicated 16-bit time-base counter with time and frequency controls
      • Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
    • Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
  • Device identification
    • Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
      • Production ID
      • Device part number (unique JTAG ID)
      • Device revision (readable by host ARM)
  • Debug interface support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
    • Supports device boundary scan
    • Supports IEEE 1500
  • DMA
    • On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
      • Transfers to and from on-chip memories
      • Transfers to and from external storage (EMIF, GPMC, slave peripherals)
  • Inter-processor communication (IPC)
    • Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox registers that generate interrupts
        • Initiators (Cortex-A8, PRCM)
      • Spinlock has 128 software-assigned lock registers
  • Security
    • Crypto hardware accelerators (AES, SHA, PKA, RNG)
  • Boot modes
    • Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
  • Package:
    • 324-pin S-PBGA-N324 package
      (GCZ suffix), 0.80-mm ball pitch

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

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Technical documentation

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Type Title Date
* Data sheet AM3358-EP Sitara™ Processor datasheet (Rev. B) 18 Apr 2019
* Errata AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 03 Jan 2017
* User guide AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 13 Dec 2019
* VID AM3358-EP VID V6215602 21 Jun 2016
* Radiation & reliability report AM3358BGCZA80EP Reliability Report 17 Dec 2015
Design guide Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) 09 Nov 2021
Application note Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 07 May 2021
White paper Time sensitive networking for industrial automation (Rev. B) 20 Jan 2021
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 16 Dec 2020
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28 Jul 2020
Application note AM335x Schematic Checklist (Rev. A) 19 Dec 2019
Application note Programmable Logic Controllers — Security Threats and Solutions 13 Sep 2019
More literature Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 30 Jul 2019
White paper Power optimization techniques for energy-efficient systems (Rev. A) 28 Jun 2019
White paper Sitara Processor Security (Rev. D) 09 May 2019
Application note AM335x Hardware Design Guide 03 May 2019
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 11 Apr 2019
Application note Common EOS pitfalls in board design 13 Feb 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 10 Jan 2019
Application note PRU Read Latencies (Rev. A) 21 Dec 2018
White paper Ensuring real-time predictability (Rev. B) 04 Dec 2018
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 07 Nov 2018
Application note PRU-ICSS / PRU_ICSSG Migration Guide 05 Nov 2018
Application note High-Speed Interface Layout Guidelines (Rev. H) 11 Oct 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Application note Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 28 Mar 2018
User guide Powering the AM335x With the TPS650250 (Rev. B) 14 Mar 2018
White paper Data concentrators: The core of energy and data management (Rev. A) 21 Feb 2018
White paper POWERLINK on TI Sitara Processors (Rev. A) 10 Jan 2018
More literature TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 19 Dec 2017
User guide TPS65910Ax User's Guide for AM335x Processors (Rev. F) 08 Dec 2017
Application note AM335x Reliability Considerations in PLC Applications (Rev. A) 27 Apr 2017
White paper Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 11 Aug 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
White paper Building automation for enhanced energy and operational efficiency (Rev. A) 26 Oct 2015
White paper Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 03 Mar 2015
User guide G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 13 Nov 2014
User guide Powering the AM335x with the TPS65217x . (Rev. I) 06 Sep 2014
White paper Mainline Linux™ ensures stability and innovation 27 Mar 2014
White paper Linaro Speeds Development in TI Linux SDKs 27 Aug 2013
White paper The Yocto Project:Changing the way embedded Linux software solutions are develop 14 Mar 2013
White paper Smart thermostats are a cool addition to the connected home 27 Sep 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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TPS65218EVM-100 — TPS65218 Evaluation Module

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bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


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COMPU-3P-SITARASOMS — Compulab Sitara SOMs

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Evaluation board

FORLX-3P-SITARA-SOMS — Forlinx Sitara SOMs

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
From: Forlinx Embedded Tech. Co., Ltd
Evaluation board

MYIR-3P-SITARASOMS — MYIR Sitara SOMs

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
From: MYIR Tech Limited
Evaluation board

OCTVO-3P-AM335X — Octavo Systems AM335x based system-in-package

Octavo Systems is the leader in providing system-in-package (SiP) based solutions to innovators around the globe. The OSD335x family of SiP devices are the fastest and most cost-effective way to develop and deploy high performance embedded systems based on the Sitara™ AM335x Arm® (...)

From: Octavo Systems
Evaluation board

PHYTC-3P-PHYBOARD-AM335X — PHYTEC phyBOARD-AM335x single board computer

The phyBOARD®-AM335x features a phyCORE-AM335x System on Module (SOM), based on the TI Sitara™ AM335x, which is directly soldered onto a carrier board PCB. This “Direct Solder Connect” (DSC) of the SOM to carrier board reduces system costs by omitting board-to-board (...)

From: PHYTEC
Evaluation board

PHYTC-3P-PHYCORE-AM335X — PHYTEC phyCORE-AM335x system on module

The phyCORE®-AM335x SOM supports the Texas Instruments Sitara™ AM335x family of processors which feature high processing performance, low power, and a highly integrated peripheral set enriched with cutting-edge graphics processing as well as real time protocol support. The 220-pin SOM (...)

From: PHYTEC
Evaluation board

TQ-3P-SITARASOMS — TQ Group system on modules for TI Arm-based processors and microcontrollers

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
From: TQ-Group
Evaluation board

VAR-3P-SITARASOMS — Variscite Sitara SOMs

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
From: Variscite
Daughter card

PRUCAPE — TI PRU Cape

The TI PRU Cape is a BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices.  The PRU core is (...)

In stock
Limit: 1
Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

In stock
Limit: 3
Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Development kit

PHYTC-3P-SOMS — PHYTEC system on modules for TI ARM-based Processors and Microcontrollers

PHYTEC is an industry-leading provider and integrator of System on Modules (SOMs), embedded middleware and design services that enable customers to bring complex products quickly and easily to market. They guide customers from design to production utilizing deep domain expertise; high-quality (...)

From: PHYTEC
Software development kit (SDK)

PROCESSOR-SDK-AM335X — Processor SDK for AM335x Sitara Processors - Linux and TI-RTOS support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
Software development kit (SDK)

TIBLUETOOTHSTACK-SDK — TI Dual-Mode Bluetooth® Stack

TI’s dual-mode Bluetooth stack enables Bluetooth + Bluetooth Low Energy and is comprised of Single Mode and Dual Mode offerings implementing the Bluetooth 4.0/4.1/4.2 specification. The Bluetooth stack is fully Bluetooth Special Interest Group (SIG) qualified, certified and royalty-free, (...)

Application software & framework

FNDRS-3P-LINUX — Secure, customizable, Linux platform for building scalable IoT and Edge devices

Foundries.io provides a secure, customizable, Linux platform for building scalable IoT and Edge devices.

FoundriesFactory is a cloud service, enabling product developers to develop, deploy and maintain Linux software, applications and services for IoT and Edge devices and fleets, over product (...)

Driver or library

PRU-ICSS-INDUSTRIAL-SW — PRU-ICSS Industrial Software for Sitara™ Processors

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)
Driver or library

SITARA-MACHINE-LEARNING — Machine learning at the edge

Our processors specialize in enabling machine learning inference at the edge, which helps reduce latency, decrease network bandwidth requirements, and address security and reliability concerns. Our processors incorporate highly efficient hardware accelerators to help you design intelligent (...)
Driver or library

TI-15.4-STACK-GATEWAY-LINUX-SDK — TI 15.4-Stack Gateway Linux Software Development Kit

The TI-15.4-Stack-Gateway-Linux Software Development Kit (SDK) provides a Linux software middleware for the TI 15.4-Stack companion solution. It includes a full Linux user-space software that runs on top of the TI Processor SDK for AM335x platform, which interfaces with the co-processor embedded (...)
Driver or library

WIND-3P-VXWORKS-LINUX-OS — Wind River Processors VxWorks and Linux operating systems

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
From: Wind River Systems
Driver or library

WIT-3P-SITARABSP — Witekio Sitara Android and Windows operating systems

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
From: Witekio
IDE, configuration, compiler or debugger

CCSTUDIO-SITARA — Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, (...)

IDE, configuration, compiler or debugger

KUNBUS-3P-INDUSTRIALCOMMS — KUNBUS - A Single Source for Multiprotocol Industrial Communications

KUNBUS is a German-based company specializing in industrial communication. KUNBUS is the ideal partner for industrial communication because KUNBUS offers pre-certified protocol solutions on Sitara™ processors as well as a full suite of additional services to meet the customer's needs.

Common (...)

From: KUNBUS
Operating system (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
From: Green Hills Software
Operating system (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
From: Mentor Graphics Corporation
Operating system (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

The QNX Neutrino® Realtime Operating System (RTOS) is a full-featured and robust RTOS designed to enable the next-generation of products for automotive, medical, transportation, military and industrial embedded systems. Microkernel design and modular architecture enable customers to create (...)
From: QNX Software Systems
Software programming tool

UNIFLASH — UniFlash stand-alone flash tool for microcontrollers, Sitara™; processors and SimpleLink™

Supported devices: CC13xx, CC25xx, CC26xx, CC3x20, CC3x30, CC3x35, Tiva, C2000, MSP43x, Hercules, PGA9xx, IWR12xx, IWR14xx, IWR16xx, IWR18xx , IWR68xx, AWR12xx, AWR14xx, AWR16xx, AWR18xx.  Command line only: AM335x, AM437x, AM571x, AM572x, AM574x, AM65XX, K2G

CCS Uniflash is a standalone tool used (...)

Software programming tool

AM335x and AMIC110 EMIF Tools

SPRCAJ0.ZIP (313 KB)
Support software

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

The Sercos III Slave Communiction Stack allows to implement the Real-time Ethernet protocol Sercos III for any kind of slave devices. The source code includes SCP (Sercos Communication Profile) and GDP (General Device Profile). In addition, the stack already includes many optional function classes (...)
From: AUTOMATA
Simulation model

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL Model
Simulation model

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL Model
Simulation model

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS Model
Simulation model

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS Model
Simulation model

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL Model
Simulation model

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL Model
Calculation tool

CLOCKTREETOOL — Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Calculation tool

PINMUXTOOL — Pin mux tool

The PinMux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or (...)
Calculation tool

POWEREST — Power Estimation Tool (PET)

Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)
Calculation tool

SITARA-DDR-CONFIG-TOOL — Sitara External Memory Interface (EMIF) tool

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Reference designs

TIDEP0043 — Acontis EtherCAT Master Stack Reference Design

The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performance TI Sitara MPUs,  it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT (...)
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Ordering & quality

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