TIDUEB8C July   2018  – March 2021 TPS274160

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LM5165
      2. 2.2.2 TLC59282
      3. 2.2.3 TPS4H160-Q1
      4. 2.2.4 INA253
      5. 2.2.5 TIOL111
    3. 2.3 System Design Theory
      1. 2.3.1 IO-Link PHY
      2. 2.3.2 Current Sink
      3. 2.3.3 Power Supply for L+
      4. 2.3.4 Power Supply
      5. 2.3.5 Pinouts
    4. 2.4 Software Frame Handler
      1. 2.4.1 PRU-ICSS IO-Link Frame-Handler
        1. 2.4.1.1 Performance Advantages and Benefits
        2. 2.4.1.2 Principle of Operation
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 IO-Link Wake-Up Pulse
        2. 3.2.2.2 L+ Turnon Behavior
        3. 3.2.2.3 Current Sink on CQ
        4. 3.2.2.4 Residue Voltage
        5. 3.2.2.5 IO-Link Physical Layer Test Summary
        6. 3.2.2.6 Current Sense on Each Port
        7. 3.2.2.7 TPS4H160 Thermal Behavior
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History

1.1 Key System Specifications

Table 1-1 Key System Specifications
PARAMETER SPECIFICATIONS DETAILS
Input voltage External 24-V power supply Section 2.3.4
Input current Depending on connected load (5 A recommended) Section 2.3.4
Output voltage 24 V Section 2.3.3
Output current per port 500 mA Section 2.3.3
Total output current 4 A Section 2.3.3
Number of IO-Link master ports 8
Number of Ethernet ports 2
Supported IO-Link data rates COM1, COM2, COM3
Supported IO-Link cycle time 400 µs
Frame handler Section 2.4.1
Oversampling factor 8 times
Sampling frequency Up to 1.8432 MSPS per channel (COM3)
Supported IO-Link transmission rates COM3, COM2, COM1
Equivalent Baud-rate 230.4 kbaud, 38.4 kbaud, 4.8 kbaud
RX buffer size 128 bytes
TX buffer size 2 x 128 bytes (double send buffer)
Start bit and bit filter Based on look-up table (can be adjusted)
Parity check Supported
T1 time (UART frame transmission delay, master) 0 Tbit
T2 time check (UART frame transmission delay, device) Supported, hard coded to 5
Ta time check (maximum response time) Supported and user adjustable by register