Figure 3-3 shows the different events that occur when sampling voltage and current, where the items in green are done by the MSPM0G1106 hardware modules.

New current samples for each phase are ready every OSR, or 1024 modulation clock cycles for this design, thus resulting in 4000 samples per second over the SPI bus to MSPM0+ MCU. The data transfer consists of two transactions: sample contains 12 Bytes, with three Bytes data on each of the two ADS131M02 channels and then another 15 Bytes, with data for one channel for the shunt and twice 0x00 00 00 data for the unused and disabled per software other two analog input channels for AMC131M03.

Suppose the most recently ready phase current and voltage samples from the ADS131M02 and AMC131M03 devices corresponds to the N^th – 1 current and voltage sample, or I_phx[N – 1] and V_phx[N – 1]. Once new samples are ready, the DRDY pin is asserted low by the ADS131M02. The falling edge on the DRDY pin on the ADS131M02 causes a GPIO port interrupt on the MSPM0+ MCU, which triggers the Port ISR, and the background process is run within the Port ISR. The AMC131M03 also raises the DRDY pin interrupt and that is served immediately after the ADS131M02 read out over SPI is finished.

Figure 3-4 shows the background process, which mainly deals with timing-critical events in the test software.

In the background process, the previously-obtained voltage samples (V_phx[N – 2]) and previously obtained current samples (I_phx[N – 2]) are stored so that these samples can be used later by the per_sample_dsp () function, which is responsible for updating the intermediate dot product quantities used to calculate metrology parameters.

After the previously-obtained voltage and current samples from ADS131M02 and AMC131M03 are stored, communication to the ADS131M02 is enabled by asserting the respective chip select signal low. The DMA is then configured to both send a request for the newest current and voltage samples (I_phx[N – 1] and
V_phx[N – 1]) of the ADS131M02 device and also to receive the data packet response from the ADS131M02. The request (transmitting dummy data of 0x00) and reception of the latest ADC data samples is done automatically by the DMA module.

Figure 3-5 shows the packet that is transmitted by the DMA of the MSPM0+ MCU and the response packet from the ADS131M02 or AMC131M03 that is received by the DMA as well. The transmission and reception packets contain four or five words, where each word is three bytes long, resulting in 12 or 15 Bytes DMA transaction over the SPI bus. Note that the ADS131M02 packet is 12 Bytes long, as only two channels with three bytes each are read out through the DMA transaction, while AMC131M03 needs 15 Bytes. The firmware handles the ADC device selection automatically and reads data out in a round-robin manner, as the firmware updates the DMA parameters for each ADC, including the packet data length and activates the correct CS line to each ADC.

When requesting the ADC data from the ADS131M02 device, the first word that has to be sent to by MSPM0+ MCU is the command word. Since the test software does not need to change the settings of the ADS131M02 or read any registers during typical ADC sample readouts, a NULL command is sent to the ADS131M02, which allows the designer to get the ADC samples from the ADS131M02 without changing the state of the device.

The actual size of the null command is 16 bits; however, since 24-bit words are used, the 16-bit command must be padded with an extra value of 0x00 at the end of the command. The NULL command word sent; therefore, has a value of 0x00 00 00. While the MSPM0+ MCU is shifting out the command word, the MCU is simultaneously shifting in the response word to the command word of the previous packet. The response word to a NULL command is the contents of the STATUS register. The contents of the STATUS register is not used in this design so the first word received from the ADS131M02 is ignored (not processed in the software code).

After writing the command word, a dummy write must be performed for each byte that is to be read. The dummy byte write is necessary to enable the SPI clock, which is necessary to read a byte from the ADS131M02 device. For each dummy byte write, a value of 0x00 is written to the SPI transmit register. Immediately after writing the command byte, writing three dummy bytes allows the MSPM0+ MCU to receive the 3-byte ADC value from channel 0 of the ADS131M02. Writing the next 3 dummy bytes gets the ADC data for channel 1 and writing the next three dummy bytes gets the CRC word. The CRC word is 24-bits; however, note that the actual CRC is only 16 bits, which are placed in the most significant bits of the 24-bit word. As a result, when parsing the CRC word, the last byte is not needed (note though that the dummy write for this zero-padded byte must still be sent though for proper ADS131M02 operation).

Whenever the DMA has received the entire I_phx[N – 1] packet, the DMA ISR is automatically called. Within the ISR, the CRC is calculated over the three command and the ADC channel data words (3 × 3 = 9 Bytes in total). This CRC calculation can be done in two modes: either using the CRC module of the MSPM0G110 MCU or using the memcpy() function to move the 9 Bytes ADC data to a special memory area where CRC16 is auto-calculated.

Immediately after the SPI data from AMC131M03 is read out, but using the NULL command and three channels of 24-bit data and CRC16 with a padded 0x00 Byte. This completes the read in of the current samples I_phx[N – 1] of the AMC131M03 device, then the CRC16 checksum is also checked.

See the ADS_verifyADSCRC() and AMC_verifyAMCCRC() routines for details of the CRC16 check implementation. The memcpy() implementation achieves almost 5 × faster calculation than using the CRC16 registers with bytewise feed and is hence used by default. The CRC module can be fed with 8- or 16-bit data, and since there are nine bytes total, the CRC module is being updated byte for byte. Once the CRC has been calculated over the packet, the check is compared to the CRC obtained in the packet sent from the ADS131M02. The sent CRC is parsed from Bytes 10 and 11 (the last Byte 12 is the zero-padding for CRC16, so this value gets ignored).

If the calculated CRC and the parsed CRC are equal, then the CRC check is correct and the ADC data is parsed to get the values of the voltage and current samples at time N – 1. Two variables are used to count the good and bad CRC16 packets for each ADC, called crcPassCount and crcFailCount. The parsed voltage and current samples are put in temporary buffers so that this information is used when the per_sample_dsp() function is called at the next interrupt. When the SPI transfer over DMA ends, the CS (chip select) line is automatically pulled back high again from the MSPM0+ MCU to properly reset the AMC131M03 communication before the next time current samples are ready for readout.

In parallel to transferring the latest current and voltage samples I_phx[N – 1] and V_phx[N – 1] to the MSPM0+ MCU using the DMA channels, the ADS131M02 is already sampling the next voltage (V_phx[N]) and current samples (I_phx[N]) while the test software performs per-sample processing on the earlier voltage (V_phx[N – 2]) and current samples (I_phx[N – 2] ) obtained from the ADS131M02 and AMC131M03. This per-sample processing is used to update the intermediate dot product quantities that are used to calculate the metrology parameters. After sample processing, the background process uses the per_sample_energy_pulse_processing for the calculation and output of energy-proportional pulses. The test software exits from the port ISR once the per_sample_energy_pulse_processing is completed.

In summary there are two SPI read data cycles during a single DRDY cycle, the ADS131M02 device is read out first and then the AMC131M03. The only difference between these two SPI transactions is that ADS131M02 has two channels while AMC131M03 has three, so the SPI data packet length is either 12 Bytes or 15 Bytes total.