TIDUF72 August   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
    2. 1.2 End Equipment
    3. 1.3 Electricity Meter
    4. 1.4 Power Quality Meter, Power Quality Analyzer
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Magnetic Tamper Detection With TMAG5273 Linear 3D Hall-Effect Sensor
      2. 2.2.2 Analog Inputs of Standalone ADCs
      3. 2.2.3 Voltage Measurement Analog Front End
      4. 2.2.4 Analog Front End for Current Measurement
    3. 2.3 Highlighted Products
      1. 2.3.1 AMC131M03
      2. 2.3.2 ADS131M02
      3. 2.3.3 MSPM0G1106
      4. 2.3.4 TMAG5273
      5. 2.3.5 ISO6731
      6. 2.3.6 TRS3232E
      7. 2.3.7 TPS709
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1  Software Requirements
      2. 3.1.2  UART for PC GUI Communication
      3. 3.1.3  Direct Memory Access (DMA)
      4. 3.1.4  ADC Setup
      5. 3.1.5  Foreground Process
      6. 3.1.6  Formulas
        1. 3.1.6.1 Standard Metrology Parameters
        2. 3.1.6.2 Power Quality Formulas
      7. 3.1.7  Background Process
      8. 3.1.8  Software Function per_sample_dsp()
      9. 3.1.9  Voltage and Current Signals
      10. 3.1.10 Pure Waveform Samples
      11. 3.1.11 Frequency Measurement and Cycle Tracking
      12. 3.1.12 LED Pulse Generation
      13. 3.1.13 Phase Compensation
    2. 3.2 Test Setup
      1. 3.2.1 Power Supply Options and Jumper Setting
      2. 3.2.2 Electricity Meter Metrology Accuracy Testing
      3. 3.2.3 Viewing Metrology Readings and Calibration
        1. 3.2.3.1 Calibrating and Viewing Results From PC
      4. 3.2.4 Calibration and FLASH Settings for MSPM0+ MCU
      5. 3.2.5 Gain Calibration
      6. 3.2.6 Voltage and Current Gain Calibration
      7. 3.2.7 Active Power Gain Calibration
      8. 3.2.8 Offset Calibration
      9. 3.2.9 Phase Calibration
    3. 3.3 Test Results
      1. 3.3.1 Energy Metrology Accuracy Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
      4. 4.1.4 Layout Prints
      5. 4.1.5 Altium Project
      6. 4.1.6 Gerber Files
      7. 4.1.7 Assembly Drawings
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors

3.1.8 Software Function per_sample_dsp()

Figure 3-6 shows the flowchart for the per_sample_dsp() function. The per_sample_dsp() function is used to calculate intermediate dot product results that are fed into the foreground process for the calculation of metrology readings. Both voltage and current samples are processed and accumulated in dedicated 64-bit registers. Per-phase active power and reactive power are also accumulated in 64-bit registers.

TIDA-010944 per_sample_dsp () FunctionFigure 3-6 per_sample_dsp () Function

After CYCLES_PER_COMPUTATION number of cycles (10 cycles if FNOM = 50Hz and 12 cycles if FNOM = 60Hz) have been accumulated, the background process triggers the foreground function to calculate the final values of RMS voltage and current; active, reactive, and apparent powers; active, reactive, and apparent energy; frequency; power factor; fundamental voltage, fundamental current, fundamental active power, fundamental reactive power, and fundamental apparent power; voltage underdeviation and voltage overdeviation; and voltage THD and current THD. In the software, there are two sets of dot products: at any given time, one is used by the foreground for calculation and the other used as the working set by the background. After the background process has sufficient samples, the process swaps the two dot products so that the foreground uses the newly acquired dot products that the background process just calculated and the background process uses a new empty set to calculate the next set of dot products.

Whenever there is a leading-edge zero-crossing (− to + voltage transition) on a voltage channel, the per_sample_dsp() function is also responsible for updating the frequency (in samples per cycle) of the corresponding phase and triggering the calculation of the foreground of the 1-cycle VRMS reading. This 1-cycle VRMS reading is a different calculation than the VRMS reading that is updated every CYCLES_PER_COMPUTATION number of cycles. The 1-cycle VRMS reading is specifically used for updating the sag, swell, and interruption state variables. The 1-cycle VRMS calculation uses the same dot-product swapping scheme as the scheme used for the CYCLES_PER_COMPUTATION dot products.

The per_sample_dsp() function is also responsible for outputting a voltage zero crossing pin (optional). Whenever there is a negative to positive zero crossing on a voltage channel and the corresponding 1-cycle VRMS reading of the voltage channel is greater than the interruption threshold, a falling edge is asserted on this pin. If there is a positive to negative zero crossing on a voltage channel and the 1-cycle VRMS reading of the voltage channel is greater than the interruption threshold, a rising edge is asserted on this pin. To reduce the impact of outputting the zero crossing pin on the accuracy of the design, the zero crossing output needs to not be selected to be on a GPIO pin connected to a LED.

The following sections describe the various elements of electricity measurement in the per_sample_dsp() function.