TIDUFC2 April 2025
The connection between the TX7516 and the TMUX9832 can be either star or daisy-chain. The turn-on of the TMUX channel in the daisy-chain path clearly causes large impedance discontinuities and bad signal reflections. The star routing topology between the TX7516 and TMUX9832 definitely causes pulser signal reflections. The worst-case scenario is that the signal reflection ringing exceeds the input limit of the TMUX9832 (maximum ±120V); therefore, following the simulation results before PCB routing and components placements is the best design practice. This section shows the transient simulation results based on the TMUX9832 IBIS model using Advanced Design Systems (ADS). Table 2-4 shows the simulation parameters.
| PARAMETERS | ADS SETUP |
|---|---|
| Step input sources | Vpeak = 100V, Vrise = 16.6ns, tDelay = 10ns |
| PCB layers | 16, MLSUBSTRATE16 set same with PCB stackup |
| PCB Trace | ML1CTL_C trace length set to 80mm, trace on top layer and refer to MLSUBSTRATE16. Width = 5mil. |
| Load | 220Ω | 220pF at TMUX9832 output pin |
Figure 2-16 shows the daisy-chain schematic and Figure 2-17 shows the star connection schematic.
Figure 2-18 and Figure 2-19 show the simulation results. These results indicate that a maximum peak ringing visible at the TMUX9832 input reaches 107.546V for a 100V power supply when connected as tree. The maximum peak ringing of the daisy-chain connection is already over 120.086V for same power supply, which exceeds the input voltage limit of the TMUX9832. To suppress ringing on the TMUX9832 input, limit PCB trace lengths as short as possible and maintain consistency with pre-layout simulation results.
Figure 2-20 shows the component placement.

Figure 2-21 shows the flows of how the input and output signals to the TMUX were optimized. The red arrows indicate the pulse input direction and the yellow arrows indicate the pulse output. The adjacent trace spacing needs to meet the 4W–5W rule; for example, the 5mil PCB trace width and the spacing needs to be set to 20–25mils. The design goal is to maintain the same GND reference from origination to termination for the entirety of any pulser signal trace. If unable to meet this goal, via-stitch both GND planes to provide continuous grounding and uniform impedance. Place these stitching vias symmetrically within 200mils (closer is better). For BGA fan-out of TX7516 and split of GND plane, see also the TX7516 Five-Level, 16-Channel Transmitter With T/R Switch, and On-Chip Beamformer data sheet and EVM PCB layout section.
