TIDUFC2 April   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 High-Voltage Generator Circuit
      2. 2.2.2 Low-Voltage Switching Mode Power Supply
      3. 2.2.3 Sitara™ MCU AM2431 Reset and Power Rail Monitoring Circuit
      4. 2.2.4 Clock Generator
      5. 2.2.5 CMOS to LVDS Driver
      6. 2.2.6 Layout Guidance
    3. 2.3 Highlighted Products
      1. 2.3.1 TX7516
      2. 2.3.2 TMU9832
      3. 2.3.3 AM2431
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 TIDA-010256 PCB Overview
      2. 3.1.2 TIDA-010256 Connector Settings
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 High-Voltage Power Supply Output Ripple
      2. 3.4.2 Output Waveform
      3. 3.4.3 Thermal Test
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.2.3 Sitara™ MCU AM2431 Reset and Power Rail Monitoring Circuit

The AM2431 processor wakeup needs to meet specific power-up sequencing conditions. To avoid errors in the control system from a drop in the system voltage, there is additional circuit to monitor the primary power rail. TPS386000 is an open-drain, quad-supply voltage supervisor with a programmable delay and watchdog timer. Figure 2-13 shows the reset circuit schematic.


TIDA-010256 Reset Circuit Schematic

Figure 2-13 Reset Circuit Schematic

When the voltage on the specified SENSEx pin is lower than the VITN in the data sheet (typically 400mV), the corresponding reset output is asserted. In this design, the threshold voltages are 1.692V for 1.8V and 3.12V for 3.3V.

The CPU core power rail (0.85V), which is highly sensitive to voltage changes, requires additional window monitoring configuration. TPS386000 also supports window voltage monitoring design, such as shown in the schematics, where the window voltages can be calculated using the following formulas.

Equation 3. V M O N ( U V ) = 1 + R 128 R 134 + R 135 × 0.4 = ( 1 + 100 101.4 ) × 0.4   = 0.7956 V
Equation 4. VMON(OV)=1+R128+R134R135×0.4=(1+100+12.788.7) ×0.4 =0.9082V

To program a user-defined adjustable delay time, an external capacitor must be connected between CTn and GND. Use Equation 5 to calculate the adjustable delay time.

Equation 5. C C T n F = t d e l a y m s - 0.5 m s × 0.242 = 2.39822 n F

where

  • tdelay = 10.41ms

After the power rail output has been established and stabilized for a predetermined delay time, the output is asserted high with the PORZ signal, which corresponds to the logic level high of the gate logic IC SN74LVC1G11DCKR. Conversely, as soon as any power rail experiences a voltage dropout, the processor is reset.