TIDUFE2 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Fault Detection and Protection
      2. 2.2.2 Theory of Operation - Parallel LDOs Using Op Amps
      3. 2.2.3 Theory of Operation - Parallel LDOs Using Ballast Resistors
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7B7702-Q1, Automotive, Dual-Channel Antenna Low Dropout (LDO) Regulator With Current Sense
      2. 2.3.2 OPAx388 Automotive, Precision, Zero-Drift, Zero-Crossover, True Rail-to-Rail, Input/Output Operational Amplifiers
      3. 2.3.3 LMV321A-Q1 Automotive Low-Voltage Rail-to-Rail Output Operational Amplifier
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results - Parallel LDOs Using Op Amps
      1. 3.3.1 Short to Battery
      2. 3.3.2 Load Transient Response
      3. 3.3.3 Current Limit
      4. 3.3.4 Start-Up
      5. 3.3.5 Shutdown
      6. 3.3.6 Line Transient
      7. 3.3.7 PSRR
      8. 3.3.8 Thermal Performance
      9. 3.3.9 Thermal Limit Protection
    4. 3.4 Test Results - Parallel LDOs Using Ballast Resistors
      1. 3.4.1 Short to Battery
      2. 3.4.2 Load Transient Response
      3. 3.4.3 Current Limit
      4. 3.4.4 Start-Up
      5. 3.4.5 Line Transient
      6. 3.4.6 Thermal Performance
      7. 3.4.7 Thermal Limit Protection
    5. 3.5 Comparison of Results Between Parallel LDO Techniques
      1. 3.5.1 VLOAD vs ILOAD
      2. 3.5.2 PSRR
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

1.1 Key System Specifications

Table 1-1 Key System Specifications (Parallel LDO Using Op Amps)
PARAMETER SPECIFICATIONS
Input Voltage Range 4.5V to 40V
Output Voltage Range 1.5V to 35V
Optimized for Input Voltage, VIN 12V
Optimized for Output Voltage, VOUT 10V
Maximum Output Current Scalable
600mA is capable with 2 × TPS7B7702-Q1 channels using op amps
900mA is capable with 3 × TPS7B7702-Q1 channels using op amps
1.2A is capable with 4 × TPS7B7702-Q1 channels using op amps
VOUT Transient Deviation, 600mA to 1.2A to 600mA, 4 parallel channels, 1A/µs (typical)(1) +135mVPK/–113mVPK
VOUT Transient Deviation, 600mA to 1.2A to 600mA, 4 parallel channels, 0.1A/µs (typical)(1) +132mVPK/–109mVPK
VOUT Transient Deviation, 450mA to 900mA to 450mA, 1A/µs (typical)(1) +114mVPK/–96mVPK
VOUT Transient Deviation, 450mA to 900mA to 450mA, 0.1A/µs (typical)(1) +113mVPK/–94mVPK
VOUT Transient Deviation, 300mA to 600mA to 300mA, 1A/µs (typical)(1) +85mVPK /–78mVPK
VOUT Transient Deviation, 300mA to 600mA to 300mA, 0.1A/µs (typical)(1) +82mVPK /–79mVPK
Load Regulation +16.7mV/A
(1) Each TPS7B7702-Q1 LDO has one 10µF ceramic capacitor on the OUT pin to GND.
Table 1-2 Key System Specifications (Parallel LDO Using Ballast Resistors)
PARAMETER SPECIFICATIONS
Input Voltage Range 4.5V to 40V
Output Voltage Range 1.5V to 35V
Optimized for Input Voltage, VIN 12V
Optimized for Output Voltage, VOUT 10V
Maximum Output Current(1) 500mA (2 × TPS7B7702-Q1(2) channels using ballast resistors)
VOUT Transient Deviation, 300mA to 600mA to 300mA, CFF = Uninstalled, 1A/µs (typical)(1) +135mVPK/–326mVPK
VOUT Transient Deviation, 300mA to 600mA to 300mA, CFF = 22nF, 1A/µs (typical)(1) +28mVPK/–226mVPK
VOUT Transient Deviation, 300mA to 600mA to 300mA, CFF = Uninstalled, 0.1A/µs (typical)(1) +139mVPK/–323mVPK
VOUT Transient Deviation, 300mA to 600mA to 300mA, CFF = 22nF, 0.1A/µs (typical)(1) +29mVPK/–223mVPK
Ballast Resistor 1.33Ω
Load Regulation –662mV/A
(1) Theoretically, there is no limit to the number of LDO channels which can be paralleled using ballast resistors. The reference voltage presents a significant error term in parallel LDOs and while the internal reference is shared among the two LDO channels inside the TPS7B7702-Q1 package, this is not true for separate TPS7B7702-Q1 packages. For this reason, TI recommends limiting the number of parallel TPS7B7702-Q1 LDO channels to two when using the ballast resistor technique.
(2) Each TPS7B7702-Q1 LDO has one 10µF ceramic capacitor on the OUT pin to GND, before the ballast resistor. There is one additional 10µF ceramic capacitor after the ballast resistor.