TIDUFE2 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Fault Detection and Protection
      2. 2.2.2 Theory of Operation - Parallel LDOs Using Op Amps
      3. 2.2.3 Theory of Operation - Parallel LDOs Using Ballast Resistors
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS7B7702-Q1, Automotive, Dual-Channel Antenna Low Dropout (LDO) Regulator With Current Sense
      2. 2.3.2 OPAx388 Automotive, Precision, Zero-Drift, Zero-Crossover, True Rail-to-Rail, Input/Output Operational Amplifiers
      3. 2.3.3 LMV321A-Q1 Automotive Low-Voltage Rail-to-Rail Output Operational Amplifier
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results - Parallel LDOs Using Op Amps
      1. 3.3.1 Short to Battery
      2. 3.3.2 Load Transient Response
      3. 3.3.3 Current Limit
      4. 3.3.4 Start-Up
      5. 3.3.5 Shutdown
      6. 3.3.6 Line Transient
      7. 3.3.7 PSRR
      8. 3.3.8 Thermal Performance
      9. 3.3.9 Thermal Limit Protection
    4. 3.4 Test Results - Parallel LDOs Using Ballast Resistors
      1. 3.4.1 Short to Battery
      2. 3.4.2 Load Transient Response
      3. 3.4.3 Current Limit
      4. 3.4.4 Start-Up
      5. 3.4.5 Line Transient
      6. 3.4.6 Thermal Performance
      7. 3.4.7 Thermal Limit Protection
    5. 3.5 Comparison of Results Between Parallel LDO Techniques
      1. 3.5.1 VLOAD vs ILOAD
      2. 3.5.2 PSRR
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3.2 Test Setup

The TIDA-050096 reference design showcases two methods to paralleling the TPS7B7702-Q1 LDOs. All components needed for evaluation are populated: input, output, VCC, sense and feedforward capacitors are installed, as well as error, current limit, feedback, and sense resistors are also installed. See also the TPS7B770x-Q1, Automotive, Single- and Dual-Channel Antenna LDO With Current Sense data sheet for guidance on selecting these components. The TIDA-050096 reference design is configured for 12V input, 10V output, with a range of load-current options.

The first method to parallel the TPS7B7702-Q1 LDOs uses op amps to current share the LDOs. Two different op amps are used to characterize performance of the reference design (OPA388-Q1 and LMV321A-Q1). The compensation capacitors and resistors to maintain stability with the addition of the new feedback loop are installed. The TIDA-050096 reference design supports up to four paralleled LDO channels to obtain up to 1.2A output current with all of the features already included in the single TPS7B7701-Q1 LDO.

TIDA-050096 2 ×–4 × Parallel LDO Channels Using Op Amps and Current Sensing Figure 3-1 2 ×–4 × Parallel LDO Channels Using Op Amps and Current Sensing

Four LDO channels is not the limit with this technique. If more current is needed in the end application, additional LDO channels can be paralleled using the op-amp technique, as necessary.

The second method to parallel the TPS7B7702-Q1 LDOs uses ballast resistors. Recommended ballast resistors are installed, as well as an extra load capacitor. While there is no fundamental limit to the number of LDOs which can be paralleled using ballast resistors, because a single reference cannot be shared among TPS7B7702-Q1 devices in different packages, the paralleled LDOs across packages experience an increased error voltage. This increase in error voltage directly correlates to an increase in ballast resistance. TI recommends limiting the number of parallel TPS7B7702-Q1 channels to the two LDOs inside the package and if more LDOs are needed, to use the op-amp parallel method.

TIDA-050096 2 × Parallel LDO Channels Using Ballast Resistors Figure 3-2 2 × Parallel LDO Channels Using Ballast Resistors

The TPS7B7702-Q1 LDO channels can be enabled or disabled by using the 3-pin headers (J7, J8, J9, J13 for the op-amp method, or J23 and J26 for the ballast resistor method).

  • Tie the center pin of the 3-pin header to Vin to enable the device
  • Tie the center pin of the 3-pin header to a GND to disable the device

Test points are provided to measure the ILIM voltage of each LDO channel to confirm each is sharing the load current equally. A 2-pin header connects VCC of the TPS7B7702-Q1 to the positive power rail of the op amp, and can be used to measure the current draw of the op amp. The VCC pin can source up to 15mA current draw from external circuitry. J2 (parallel LDOs using op amps) or J25 (parallel LDOs using ballast resistors) can be used to connect external loading for evaluation.

The parallel LDOs using op-amp designs include additional connectors for evaluation. MMCX connectors are available to measure VIN and VOUT. Test points are available to measure VERR for each package (VERR1 for the top IC and VERR2 for the bottom IC). A 2-pin header can be used to short VERR1 to VERR2 which is how the measurements in this design guide are captured.