Ballast resistors provide an easy way to connect multiple voltage sources together to supply power to a common load. Minimizing the voltage difference, called the error voltage V_E, at the output of each individual LDO is critical. As LDO accuracy improves, the size of the ballast resistor can be reduced.

Each TPS7B7702-Q1 has two internal LDO channels which share an internal reference. This eliminates the dominant source of error in paralleled LDOs using ballast resistors, which is the difference among reference voltages. The remaining sources of error come from the ballast resistors, the internal output field-effect transistor (FET), and the amplifier. These errors show up as the offset voltage, which is also a function of line and load. The offset voltage, combined with the tolerance in the setpoint feedback resistors, make up the total error V_E of each LDO. To achieve the smallest current-sharing error between the different LDOs, use 0.1% (or better) tolerance feedback resistors. The offset voltage is magnified by the internal error amplifier gain, which is set as a function of the necessary output voltage to determine V_OUT. In this reference design, all ballast resistors are configured to be the same value, for simplicity.

Traditionally, the ballast resistance is chosen using Equation 1 to set the current imbalance I_MAX of the parallel LDOs.

This formula does not account for the load voltage, V_LOAD, which is also a requirement for most modern power supplies designed with parallel LDOs. Texas Instruments has modernized the design and analysis of parallel LDOs using ballast resistors (see references [4] and [6]), and a downloadable software tool has been developed to design R_B for our LDOs against a set of system requirements (see reference [5]). The parallel TPS7B7702-Q1 devices using ballast resistors are designed by using the downloadable software tool to assess the system requirements and design the necessary ballast resistance.

In addition to I_OUTn and V_LOAD, other system requirements can require using a parallel LDO topology such as noise, PSRR, dropout and thermal limitations. In brief, parallel LDOs using ballast resistors:

1. Reduce the system noise by a factor of the square root of the number of LDOs in parallel
2. Increase the system PSRR when compared with using a single LDO
3. Reduce the dropout requirement by spreading the load current across multiple LDOs
4. Decrease the junction temperature of the linear regulator by spreading the power dissipation across multiple LDOs

For a detailed discussion on all of these system requirements, how parallel LDOs using ballast resistors can increase performance, and how many parallel LDOs are needed for the system requirements, see reference [4], [5], and [6].

Ballast resistors are typically employed as either a PCB trace or a discrete resistor. In general, PCB trace resistors favor applications which are low cost. PCB trace resistors are also a good choice for applications which operate in a narrow temperature range or experience very high temperatures. Trace resistors are an excellent choice where multiple low-current devices are paralleled together (such as are seen in high-voltage LDOs, which are typically limited in the available output currents).

Discrete resistors are a good choice for applications which require maximum performance (where output voltage tolerance and transient responses are critical). A discrete resistor approach also favors applications where high-current devices are being paralleled (such as low-voltage LDOs, where high-current devices are readily available). Designing with a discrete ballast resistor becomes challenging when ambient temperatures exceed 125°C, and it is difficult to use discrete ballast resistors above 150°C. For a detailed discussion on ballast resistor analysis and design, see reference [4].