SLWU086C November   2013  – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84


  1.   TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
      2. 2.2 Switches, Jumpers, and LEDs
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
      3. 2.3 LEDs
        1. 2.3.1 Power and Configuration LEDs
        2. 2.3.2 Status LEDs
        3. 2.3.3 Connectors
          1. SMA Connectors
          2. FPGA Mezzanine Card (FMC) Connector
          3. JTAG Connectors
          4. USB I/O Connection
    4. 3 Software Start-Up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
    5. 4 Downloading Firmware
  2.   Revision History

TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide

The TI TSW14J56 evaluation module (EVM) is a next generation pattern generator and data capture card used to evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the TSW14J56 can be used to demonstrate datasheet performance specifications. Using Altera JESD204B IP cores, the TSW14J56 can be dynamically configurable to support lane speeds from 600 Mbps to 12.5 Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame with one firmware build. Together with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs.