ADS42JB69

ACTIVE

Dual-Channel, 16-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Top

Product details

Parameters

Sample rate (Max) (MSPS) 250 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1700 Architecture Pipeline SNR (dB) 75.9 ENOB (Bits) 12.1 SFDR (dB) 95 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

open-in-new Find other High-speed ADCs (>10MSPS)
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 20
Type Title Date
* Datasheet ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F) Dec. 22, 2014
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
User guide ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module User's Guide (Rev. D) Feb. 08, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
User guide TSW14J10 FMC-USB Interposer Card User's Guide (Rev. B) Sep. 28, 2016
Application note Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai May 02, 2016
User guide TSW14J50 User's Guide (Rev. A) Apr. 25, 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) Jan. 11, 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application note Analog Applications Journal 2Q 2015 Apr. 28, 2015
Application note JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) Mar. 19, 2015
User guide Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs Oct. 04, 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application note LMK04828 as a Clock Source for the ADS42JB69 Nov. 14, 2012
User guide JESD204B Start Up: Configuration Requirements and Debug Oct. 26, 2012
User guide Understanding JESD204B Subclasses and Deterministic Latency Oct. 26, 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
Description

The ADS42JB69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB69 and LMK04828 clock jitter cleaner. The ADS42JB69 is a low power, 16-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS42JB69 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
EVALUATION BOARD Download
document-generic User guide
99
Description

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

Features
  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • Software development

    FIRMWARE Download
    JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
    TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
    Features
    • Compatible with JEDEC JESD204a/b/c protocols
    • Supports subclass 1 deterministic latency and multidevice synchronization
    • Supported lane rates
      • Up to 16.375 Gbps in 8b/10b mode
      • Up to 20 Gbps in 64b/66b mode
    • Supports all protocol related error detection and reporting features
    • Integrated transport layer (...)
    FIRMWARE Download
    SLAC690C.ZIP (5251 KB)
    GUI FOR EVALUATION MODULE (EVM) Download
    SLAC544D.ZIP (162552 KB)
    SUPPORT SOFTWARE Download
    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    Features
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)

    Design tools & simulation

    SIMULATION MODEL Download
    SLAM187.ZIP (174 KB) - IBIS Model
    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    SCHEMATIC Download
    SLRR006.ZIP (9208 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGC) 64 View options

    Ordering & quality

    Information included:
    • RoHS
    • REACH
    • Device marking
    • Lead finish/Ball material
    • MSL rating/Peak reflow
    • MTBF/FIT estimates
    • Material content
    • Qualification summary
    • Ongoing reliability monitoring

    Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

    Support & training

    TI E2E™ forums with technical support from TI engineers

    Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

    If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

    Videos