Product details

Sample rate (Max) (MSPS) 250 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1700 Architecture Pipeline SNR (dB) 75.9 ENOB (Bits) 12.1 SFDR (dB) 95 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 250 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1700 Architecture Pipeline SNR (dB) 75.9 ENOB (Bits) 12.1 SFDR (dB) 95 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
  • Dual-Channel ADCs
  • 14- and 16-Bit Resolution
  • Maximum Clock Rate: 250 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two and Four Lanes Support
  • Analog Input Buffer with High-Impedance Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm VQFN-64
  • Power Dissipation: 850 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 73.3 dBFS
      • SFDR: 93 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.7 dBFS
      • SFDR: 89 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

For all available packages, see the orderable addendum at the end of the datasheet.

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Technical documentation

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Type Title Date
* Data sheet ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F) 22 Dec 2014
EVM User's guide ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module User's Guide (Rev. D) 08 Feb 2017
User guide TSW14J10 FMC-USB Interposer Card User's Guide (Rev. B) 28 Sep 2016
Application note Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai 02 May 2016
User guide TSW14J50 User's Guide (Rev. A) 25 Apr 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) 11 Jan 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Analog Design Journal Analog Applications Journal 2Q 2015 28 Apr 2015
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements 28 Apr 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mar 2015
Technical article JESD204B: Is it for you? 14 Mar 2014
User guide Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs 04 Oct 2013
Technical article JESD204B vs. LVDS in high speed data converters 20 Sep 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note LMK04828 as a Clock Source for the ADS42JB69 14 Nov 2012
User guide JESD204B Start Up: Configuration Requirements and Debug 26 Oct 2012
User guide Understanding JESD204B Subclasses and Deterministic Latency 26 Oct 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS42JB69EVM — ADS42JB69 Dual-Channel, 16-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS42JB69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB69 and LMK04828 clock jitter cleaner. The ADS42JB69 is a low power, 16-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Firmware

TSW14J10EVM Xilinx Firmware Source (Rev. C)

SLAC690C.ZIP (5251 KB)
lock = Requires export approval (1 minute)
GUI for evaluation module (EVM)

ADS42JBxx GUI v1p1 installer (Rev. D)

SLAC544D.ZIP (162552 KB)
lock = Requires export approval (1 minute)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS42JB69 IBIS Model

SLAM187.ZIP (174 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGC) 64 View options

Ordering & quality

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