The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel,
1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B
lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface
allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple
The device includes features that simplify the design of complex transmit architectures.
Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation
simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled
Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant
impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay
Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between
channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection
mechanism is available to provide PA protection in cases when the abnormal power behavior of the
input data is detected.