Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)


Product details


Resolution (Bits) 16 DAC channels 4 Interface JESD204B Sample/update rate (MSPS) 2500 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 1859 SFDR (dB) 81 Architecture Current Source Operating temperature range (C) -40 to 85 Reference: type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other High-speed DACs (>10MSPS)


  • Resolution: 16-Bit
  • Maximum Sample Rate:
    • DAC37J84: 1.6 GSPS
    • DAC38J84: 2.5 GSPS
  • Maximum Input Data Rate: 1.23GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC Synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Multi-Band Mode: Digital Summation of Independent
    Complex Signals
  • 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Terminal-Compatible with Dual-Channel DAC37J82/
    DAC38J82 Family
  • Power Dissipation: 1.8W at 2.5GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA
open-in-new Find other High-speed DACs (>10MSPS)


The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

open-in-new Find other High-speed DACs (>10MSPS)

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters datasheet (Rev. B) Mar. 24, 2014
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Application note DAC3xJ8x Device Initialization and SYSREF Configuration Sep. 27, 2017
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
User guide TSW14J10 FMC-USB Interposer Card User's Guide (Rev. B) Sep. 28, 2016
User guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design Sep. 23, 2016
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) Jun. 20, 2016
User guide DAC3XJ8XEVM User's Guide (Rev. B) Apr. 28, 2016
User guide TSW14J50 User's Guide (Rev. A) Apr. 25, 2016
User guide TSW3XJ8XEVM User's Guide (Rev. B) Mar. 09, 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) Jan. 11, 2016
User guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) Oct. 22, 2015
Application note System solution for avionics & defense Sep. 23, 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) Mar. 19, 2015
User guide Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) Sep. 15, 2014
User guide Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) Aug. 14, 2013
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) Oct. 23, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


 The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software (...)

  • Allows comprehensive testing of the DAC3XJ8X family of high-speed, JESD204B interface DACs
  • Transformer-coupled signal path enables direct performance testing of the DAC3XJ8X outputs
  • Simplified testing using the onboard LMK04828 JESD204B clocking solution for clock generation, jitter cleaning, or (...)

The TSW38J84EVM Evaluation Module is an evaluation board that allows system designers to evaluate the performance of Texas Instruments' dual transmit signal chain consisting of the DAC38J84, TRF3722, TRF3705, and the LMK04828. For ease of use as a complete dual RF transmit solution the TSW38J84EVM (...)

  • Complete bits-to-RF dual transmit signal chain solution utilizing the JESD204B interface
  • TRF3722 integrated modulator and RF synthesizer reduces solution size and simplifies layout
  • Enables evaluation of RF performance of both TRF3722 and TRF3705 modulators
  • Includes LMK04828 for onboard clock generation (...)

Software development

JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
SLAC690C.ZIP (5251 KB)
SLAC644B.ZIP (219583 KB)
SLAC661.ZIP (182158 KB)
SLWC107U.ZIP (515773 KB)
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SLAM197.ZIP (50 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design
TIDA-00409 The TSW38J84 EVM reference design provides a platform to demonstrate a wideband dual transmit solution that incorporates an integrated LO.  The reference design utilizes the 2.5 GSPS DAC38J84 device with the high performance modulators: TRF3722 (including integrated PLL/VCO) and TRF3705. The (...)
document-generic Schematic
Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs
TIDA-00996 To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
document-generic Schematic
Optimized Radar System Reference Design Using a DSP+ARM SoC
TIDEP0060 — For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a (...)
document-generic Schematic
High-Bandwidth Arbitrary Waveform Generator Reference Design: DC or AC coupled, High-Voltage output
TIDA-00684 — In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
document-generic Schematic
Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design
TIDEP0081 — For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
document-generic Schematic
66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs
TIDEP0034 For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
document-generic Schematic
High Bandwidth, High Frequency Transmitter Reference Design
TIDA-00335 This design illustrates the circuit modifications required to support high bandwidth and  high frequency applications using current source DACs like the  DAC38J84 with the TRF3704 modulator.  The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths.  The DAC38J84 (...)
document-generic Schematic

CAD/CAE symbols

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