Packaging information
| Package | Pins CFP (NBC) | 128 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 12 | JEDEC TRAY (5+1) |
Features for the ADC08D1520QML-SP
- Total Ionizing Dose 300 krad(Si)
- Single Event Latch-up 120 MeV-cm2/mg
- Single +1.9V ±0.1V Operation
- Interleave Mode for 2x Sample Rate
- Multiple ADC Synchronization Capability
- Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment
- Choice of SDR or DDR output clocking
- 1:1 or 1:2 Selectable Output Demux
- Second DCLK output
- Duty Cycle Corrected Sample Clock
- Test pattern
- Serial Interface for Extended Control
Key Specifications
- Resolution 8 Bits
- Max Conversion Rate 1.5 GSPS (min)
- Code Error Rate 10-18 (typ)
- ENOB at 748 MHz Input 7.2 Bits (typ)
- DNL ±0.15 LSB (typ)
- Power
Consumption
- Operating in 1:2 Demux Output 2.0 W (typ)
- Power Down Mode 2.9 mW (typ)
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Description for the ADC08D1520QML-SP
The ADC08D1520 is an 8–Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 2.9 mW in the Power Down Mode and is available in a 128-pin, thermally enhanced, multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range.