Product details

Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
PBGA (ZKB) 256 289 mm² 17 x 17
  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Automotive, or Extended Temperature
  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Automotive, or Extended Temperature

The device is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These include C compilers and a Windows® debugger interface for visibility into source code execution.

The device is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These include C compilers and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet AM1707 ARM® Microprocessor datasheet (Rev. E) PDF | HTML 17 Jun 2014
* Errata AM1707 ARM Microprocessor Silicon Errata (Silicon Revisions 3.0, 2.1, and 2.0) (Rev. E) 17 Jun 2014
* User guide AM1707 ARM Microprocessor Technical Reference Manual (Rev. D) 22 Sep 2016
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 Mar 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 Mar 2023
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
Application note General Hardware Design/BGA PCB Design/BGA 22 Feb 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 14 Feb 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 13 Aug 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
Application note Using the AM17xx Bootloader (Rev. C) 31 May 2012
Application note Powering the AM1705 and AM1707 With the TPS650061 (Rev. A) 18 Oct 2011
Application note AM17x Power Consumption Summary 30 Jun 2010
Application note AM17xx Pin Multiplexing Utility 01 Mar 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Software development kit (SDK)

LINUXEZSDK-SITARA — Linux EZ Software Development Kit (EZSDK) for Sitara™ Processors

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

Software development kit (SDK)

WINCESDK-AM1XOMAPL1X — Windows® Embedded Compact/CE SDK - ARM9™-based AM18x, OMAP-L13x Processor

Microsoft Windows Embedded Compact (WEC7) andCE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available fromAdeneo Embedded.

IDE, configuration, compiler or debugger

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Launch Download options
Simulation model

AM1707 ZKB BSDL Model

SPRM492.ZIP (6 KB) - BSDL Model
Simulation model

AM1707 ZKB IBIS Model (Rev. A)

SPRM493A.ZIP (176 KB) - IBIS Model
Reference designs

PR1061 — Powering the AM1705 and AM1707 with the TPS650061

Low cost integrated power solution for AM17xx processors
Test report: PDF
Package Pins CAD symbols, footprints & 3D models
PBGA (ZKB) 256 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

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