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Automotive Catalog High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrators

CD74HC4538-Q1

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Product details

Parameters

Channels (#) 2 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type Standard CMOS Output type Push-Pull IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable open-in-new Find other Monostable multivibrator (one-shot)

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Monostable multivibrator (one-shot)

Features

  • Qualified for Automotive Applications
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From the Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output Pulse Widths
  • Schmitt-Trigger Input on A and B Inputs
  • Retrigger Time Is Independent of CX
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

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Description

The CD74HC4538 is a dual retriggerable/resettable precision monostable multivibrator for fixed-voltage timing applications. An external resistor (RX) and external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing-edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to GND and an unused B input should be tied to VCC. On power up, the IC is reset. Unused resets and sections must be terminated. In normal operation, the circuit retriggers on the application of each new trigger pulse. To operate in the nontriggerable mode, Q is connected to B\ when leading-edge triggering (A) is used, or Q is connected to A when trailing-edge triggering (B) is used. The period τ can be calculated from τ = (0.7) RX, CX; RMIN is 5 kΩ. CMIN is 0 pF.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator datasheet (Rev. A) Apr. 24, 2008
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Designing with the SN74LVC1G123 Monostable Multivibrator Jul. 14, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCLM120.ZIP (36 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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