Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

CDCM1802

ACTIVE

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

Order now
Data sheet

CDCM1802

ACTIVE
Data sheet Order now

Product details

Number of outputs 1 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 1600 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVPECL Input type LVPECL
Number of outputs 1 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 1600 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVPECL Input type LVPECL
VQFN (RGT) 16 9 mm² (3 mm × 3 mm)
  • Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Both LVPECL and LVCMOS Outputs
  • 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • 3.3-V Power Supply (2.5-V Functional)
  • Signaling Rate Up to 800-MHz LVPECL and
    200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 16-Pin VQFN Package (3.00 mm × 3.00 mm)
  • Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Both LVPECL and LVCMOS Outputs
  • 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • 3.3-V Power Supply (2.5-V Functional)
  • Signaling Rate Up to 800-MHz LVPECL and
    200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 16-Pin VQFN Package (3.00 mm × 3.00 mm)

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

filter Find other Clock buffers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device.
LMK01000 ACTIVE 1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs 1:8, LVPECL/LVDS buffer divider
CDCM1804 ACTIVE 1:3 LVPECL clock buffer & LVCMOS output & programmable divider 1:4 LVPECL buffer divider
CDCP1803 ACTIVE 1:3 LVPECL clock buffer with programable divider 1:3 LVPECL buffer divider

Technical documentation

No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O + Additional LVCMOS Output datasheet (Rev. C) PDF | HTML Jul 6, 2017
Application note CDCM1802/CDCM1804 Aug 4, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

CDCM1802 IBIS Model

SCAC051.ZIP (25 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VQFN (RGT) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos