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LMK01000

ACTIVE

1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs

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Data sheet

LMK01000

ACTIVE
Data sheet Order now

Product details

Function Differential, Fanout Additive RMS jitter (Typ) (fs) 30 Output frequency (Max) (MHz) 1600 Number of outputs 8 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 30 Features uWire Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS, LVPECL Input type LVDS
Function Differential, Fanout Additive RMS jitter (Typ) (fs) 30 Output frequency (Max) (MHz) 1600 Number of outputs 8 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 30 Features uWire Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS, LVPECL Input type LVDS
WQFN (RHS) 48 49 mm² 7 x 7

  • 30 fs additive jitter (100 Hz to 20 MHz)
  • Dual clock inputs
  • Programmable output channels (0 to 1600 MHz)
  • External synchronization
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Device LVDS Outputs LVPECL Outputs
    LMK01000 3 5
    LMK01010 8 0
    LMK01020 0 8

  • 30 fs additive jitter (100 Hz to 20 MHz)
  • Dual clock inputs
  • Programmable output channels (0 to 1600 MHz)
  • External synchronization
  • Pin compatible family of clocking devices
  • 3.15 to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Device LVDS Outputs LVPECL Outputs
    LMK01000 3 5
    LMK01010 8 0
    LMK01020 0 8

    The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

    The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

    Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

    Target Applications

  • High performance Clock Distribution
  • Wireless Infrastructure
  • Medical Imaging
  • Wired Communications
  • Test and Measurement
  • Military / Aerospace

    •

    The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

    The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

    Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

    Target Applications

  • High performance Clock Distribution
  • Wireless Infrastructure
  • Medical Imaging
  • Wired Communications
  • Test and Measurement
  • Military / Aerospace

    •
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    Technical documentation

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    Type Title Date
    * Data sheet Fam LMK01000 Fam 1.6GHz HPer Clk Buffer, Divider and Distributor datasheet (Rev. G) 15 Oct 2009
    EVM User's guide LMK01000 Evaluation Board User's Guide (Rev. B) 01 Jul 2019
    Application note AN-1821 CPRI Repeater System (Rev. A) 26 Apr 2013
    Application note Phase Synchronization with Multiple Devices and Frequencies (Rev. A) 26 Apr 2013
    Design guide Clock Conditioner Owner's Manual 10 Nov 2006

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Evaluation board

    LMK01000EVAL — 1.6 GHz Low Noise Clock Buffer, Divider, and Distributor

    The LMK01000 Evaluation Kit simplifies evaluation of the LMK01000 1.6 GHz High Performance Clock Buffer, Divider, and Distributor. The package consists of an Evaluation Board, Evaluation Board Instructions, and a cable for programming the device through a PC parallel port. CodeLoader 4 is the (...)

    Not available on TI.com
    Application software & framework

    CLOCKDESIGNTOOL — Clock Design Tool - Loop Filter & Device Configuration + Simulation

    The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
    Download
    Application software & framework

    TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

    The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
    Download
    IDE, configuration, compiler or debugger

    CODELOADER — CodeLoader Software for device register programming

    The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

    Which software do I use?

    Product

    (...)
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    Simulation model

    LMK01000 IBIS Model (Rev. A)

    SNAM019A.ZIP (31 KB) - IBIS Model
    Download
    Simulation tool

    PSPICE-FOR-TI — PSpice® for TI design and simulation tool

    PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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    Design tool

    CLOCK-TREE-ARCHITECT — Clock tree architect programming software

    Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
    Design now
    Package Pins Download
    WQFN (RHS) 48 View options

    Ordering & quality

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    Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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