CDCUN1208LP

ACTIVE

Ultra Low Power, 2:8 Fan-out Buffer with Universal Inputs and Outputs

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Product details

Parameters

Function Differential, Fanout Additive RMS jitter (Typ) (fs) 200 Output frequency (Max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 50 Features 3.3-V VCC/VDD, I2C interface, Pin programmable Operating temperature range (C) -40 to 85 Rating Catalog Output type HCSL Input type HCSL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RHB) 32 25 mm² 5 x 5 open-in-new Find other Clock buffers

Features

  • Supports PCIe Gen1, Gen2, Gen3
  • Configuration Options (Through Pins or SPI/I2C):
    • Input Type (HCSL, LVDS, LVCMOS)
    • Output Type (HCSL, LVDS, LVCMOS)
    • Signal Edge Rate (Slow, Medium, Fast)
    • Clock Input Divide Value (/1, /2, /4, /8) – IN2 Only
  • Low-Power Consumption and Power Management Features, Including 1.8-V Operation and Output Enable Control
  • Integrated Voltage Regulators to Improve PSNR
  • Excellent Additive Jitter Performance
    • 200 fs RMS (10 kHz to 20 MHz), LVDS at
      100 MHz
    • 160 fs RMS (10 kHz to 20 MHz), HCSL at
      100 MHz
  • Maximum Operating Frequency:
    • Differential Mode: up to 400 MHz
    • LVCMOS Mode: up to 250 MHz
  • ESD Protection Exceeds 2-kV HBM, 500-V CDM
  • Industrial Temperature Range (–40°C to 85°C)
  • Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)

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Description

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.

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Technical documentation

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Type Title Date
* Datasheet CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs datasheet (Rev. D) Apr. 18, 2019
User guides CDCUN1208LP EVM User's Guide Apr. 04, 2012

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
$199.00
Description

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/ single ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with clock edge rate control. One of the device inputs includes a divider that provides divide values of /1, /2, /4, and /8 (...)

Features
  • Easy-to-use evaluation module to buffer low phase noise clocks up to 400 MHz
  • Easy device programming via host-powered USB port
  • Easy device programming via control pins
  • Rapid configuration through provided EVM Control Software
  • Can be powered from the USB port, or by an external 3.3V/2.5V/1.8V power (...)
GUIS FOR EVALUATION MODULES (EVM) Download
SCAC133.ZIP (1245 KB)

Design tools & simulation

SIMULATION MODELS Download
SCAM057.ZIP (94 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RHB) 32 View options

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