This 21 mΩ, 20 V device is designed to deliver the lowest on resistance and gate charge in a small 1.5 mm × 1.5 mm chip scale package with excellent thermal characteristics in an ultra-low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | CSD25202W15 20-V P-Channel NexFET Power MOSFET datasheet (Rev. A) | PDF | HTML | Jul 16, 2014 |
| Application brief | Estimating Leakage Currents of Power MOSFETs | PDF | HTML | Oct 31, 2025 | |
| Application note | MOSFET Support and Training Tools (Rev. G) | PDF | HTML | Oct 27, 2025 | |
| Application note | Semiconductor and IC Package Thermal Metrics (Rev. D) | PDF | HTML | Mar 25, 2024 | |
| Application note | Using MOSFET Transient Thermal Impedance Curves In Your Design | PDF | HTML | Dec 18, 2023 | |
| Application note | Solving Assembly Issues with Chip Scale Power MOSFETs | PDF | HTML | Dec 14, 2023 | |
| Application note | Using MOSFET Safe Operating Area Curves in Your Design | PDF | HTML | Mar 13, 2023 | |
| Application brief | Tips for Successfully Paralleling Power MOSFETs | PDF | HTML | May 31, 2022 | |
| Application note | AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) | Jun 14, 2019 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| DSBGA (YZF) | 9 | Ultra Librarian |
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