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CSD25501F3

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-20-V, P channel NexFET™ power MOSFET, single LGA 0.6 mm x 0.7 mm, 76 mOhm, gate ESD protection

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Data sheet

CSD25501F3

ACTIVE
Data sheet Order now

Product details

VDS (V) -20 VGS (V) -20 Type P-channel Configuration Single Rds(on) at VGS=4.5 V (max) (mΩ) 76 Rds(on) at VGS=2.5 V (max) (mΩ) 125 VGSTH typ (typ) (V) -0.75 QG (typ) (nC) 1.02 QGD (typ) (nC) 0.09 QGS (typ) (nC) 0.45 ID - silicon limited at TC=25°C (A) 3.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
VDS (V) -20 VGS (V) -20 Type P-channel Configuration Single Rds(on) at VGS=4.5 V (max) (mΩ) 76 Rds(on) at VGS=2.5 V (max) (mΩ) 125 VGSTH typ (typ) (V) -0.75 QG (typ) (nC) 1.02 QGD (typ) (nC) 0.09 QGS (typ) (nC) 0.45 ID - silicon limited at TC=25°C (A) 3.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
PICOSTAR (YJN) 3 0.414 mm² (0.69 mm × 0.6 mm)
  • Low on-resistance
  • Ultra-low Qg and Qgd
  • Ultra-small footprint
    • 0.7mm × 0.6mm
  • Low profile
    • 0.22mm max height
  • Integrated ESD protection diode
  • Lead and halogen free
  • RoHS compliant
  • Low on-resistance
  • Ultra-low Qg and Qgd
  • Ultra-small footprint
    • 0.7mm × 0.6mm
  • Low profile
    • 0.22mm max height
  • Integrated ESD protection diode
  • Lead and halogen free
  • RoHS compliant

This –20V, 64mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. The integrated 10kΩ clamp resistor (RC) allows the gate voltage (VGS) to be operated above the maximum internal gate oxide value of –6V, depending on duty cycle. The gate leakage (IGSS) through the diode increases as VGS is increased above –6V.

This –20V, 64mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. The integrated 10kΩ clamp resistor (RC) allows the gate voltage (VGS) to be operated above the maximum internal gate oxide value of –6V, depending on duty cycle. The gate leakage (IGSS) through the diode increases as VGS is increased above –6V.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet CSD25501F3 –20V P-Channel FemtoFET™ MOSFET datasheet (Rev. C) PDF | HTML Jun 24, 2024
Application brief Estimating Leakage Currents of Power MOSFETs PDF | HTML Oct 31, 2025
Application note MOSFET Support and Training Tools (Rev. G) PDF | HTML Oct 27, 2025
Application note Semiconductor and IC Package Thermal Metrics (Rev. D) PDF | HTML Mar 25, 2024
Application note Using MOSFET Transient Thermal Impedance Curves In Your Design PDF | HTML Dec 18, 2023
Application note Solving Assembly Issues with Chip Scale Power MOSFETs PDF | HTML Dec 14, 2023
Application note Using MOSFET Safe Operating Area Curves in Your Design PDF | HTML Mar 13, 2023
Application brief Tips for Successfully Paralleling Power MOSFETs PDF | HTML May 31, 2022
Design guide FemtoFET Surface Mount Guide (Rev. D) Jul 7, 2016

Design & development

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Support software

LOAD-SWITCH-FET-LOSS-CALC — Power Loss Calculation Tool for Load Switch

Quickly trade off size, cost and performance to select the optimal MOSFET based on application conditions.
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Simulation model

CSD25501F3 Unencrypted PSpice Model (Rev. A)

SLPM337A.ZIP (4 KB) - PSpice model
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Reference design

TIDA-010070 — Protected DC-bus input power and control power supply reference design for low-voltage servo drives

This reference design uses an ORing controller, the LM5050-1 to provide protection against reverse polarity and reverse current. In conjunction, the LM5069 hot swap controller is used for overcurrent, over voltage, under voltage protection, and inrush current limitation. The design also features (...)
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