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CSD75207W15

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-20-V, P channel NexFET™ power MOSFET, dual Common Source WLP 1.5 mm x 1.5 mm, 27 mOhm, gate ESD pro

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Data sheet

CSD75207W15

ACTIVE
Data sheet Order now

Product details

VDS (V) -20 VGS (V) -6 Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 27 Rds(on) at VGS=2.5 V (max) (mΩ) 39 Rds(on) at VGS=1.8 V (max) (mΩ) 81 Id peak (max) (A) -24 Id max cont (A) -3.9 QG (typ) (nC) 2.9 QGD (typ) (nC) 0.4 QGS (typ) (nC) 0.7 VGSTH typ (typ) (V) -0.8 ID - silicon limited at TC=25°C (A) 3.9 Logic level Yes Operating temperature range (°C) -55 to 150 Rating Catalog
VDS (V) -20 VGS (V) -6 Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 27 Rds(on) at VGS=2.5 V (max) (mΩ) 39 Rds(on) at VGS=1.8 V (max) (mΩ) 81 Id peak (max) (A) -24 Id max cont (A) -3.9 QG (typ) (nC) 2.9 QGD (typ) (nC) 0.4 QGS (typ) (nC) 0.7 VGSTH typ (typ) (V) -0.8 ID - silicon limited at TC=25°C (A) 3.9 Logic level Yes Operating temperature range (°C) -55 to 150 Rating Catalog
DSBGA (YZF) 9 3.0625 mm² 1.75 x 1.75
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1.5-mm × 1.5-mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection >4 kV
    • HBM JEDEC standard JESD22-A114
  • Pb and Halogen Free
  • RoHS Compliant
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1.5-mm × 1.5-mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection >4 kV
    • HBM JEDEC standard JESD22-A114
  • Pb and Halogen Free
  • RoHS Compliant

The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182.

The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182.
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Technical documentation

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* Data sheet CSD75207W15 Dual P-Channel NexFET Power MOSFET datasheet (Rev. A) PDF | HTML 12 Jun 2014
Application note MOSFET Support and Training Tools (Rev. C) PDF | HTML 22 Nov 2023
Application note Using MOSFET Safe Operating Area Curves in Your Design PDF | HTML 13 Mar 2023
Application note Solving Assembly Issues with Chip Scale Power MOSFETs PDF | HTML 21 Oct 2022
Application note Tips for Successfully Paralleling Power MOSFETs PDF | HTML 31 May 2022
More literature WCSP Handling Guide 07 Nov 2019
Application note AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) 14 Jun 2019
Technical article Understanding the benefits of “lead-free” power MOSFETs 08 Feb 2019
Technical article Wireless power during the zombie apocalypse 28 Oct 2016
Application note Semiconductor and IC Package Thermal Metrics (Rev. C) PDF | HTML 19 Apr 2016
Technical article When to use load switches in place of discrete MOSFETs 03 Feb 2016
Technical article 48V systems: Driving power MOSFETs efficiently and robustly 08 Oct 2015

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DSBGA (YZF) 9 View options
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