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CSD75207W15

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-20-V, P channel NexFET™ power MOSFET, dual Common Source WLP 1.5 mm x 1.5 mm, 27 mOhm, gate ESD pro

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Data sheet

CSD75207W15

ACTIVE
Data sheet Order now

Product details

VDS (V) -20 VGS (V) -6 Type P-channel Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 27 Rds(on) at VGS=2.5 V (max) (mΩ) 39 VGSTH typ (typ) (V) -0.8 QG (typ) (nC) 2.9 QGD (typ) (nC) 0.4 QGS (typ) (nC) 0.7 ID - silicon limited at TC=25°C (A) 3.9 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
VDS (V) -20 VGS (V) -6 Type P-channel Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 27 Rds(on) at VGS=2.5 V (max) (mΩ) 39 VGSTH typ (typ) (V) -0.8 QG (typ) (nC) 2.9 QGD (typ) (nC) 0.4 QGS (typ) (nC) 0.7 ID - silicon limited at TC=25°C (A) 3.9 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
DSBGA (YZF) 9 3.0625 mm² (— mm × — mm)
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1.5-mm × 1.5-mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection >4 kV
    • HBM JEDEC standard JESD22-A114
  • Pb and Halogen Free
  • RoHS Compliant
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1.5-mm × 1.5-mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection >4 kV
    • HBM JEDEC standard JESD22-A114
  • Pb and Halogen Free
  • RoHS Compliant

The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182.

The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182.
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Technical documentation

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* Data sheet CSD75207W15 Dual P-Channel NexFET Power MOSFET datasheet (Rev. A) PDF | HTML Jun 12, 2014
Application brief Estimating Leakage Currents of Power MOSFETs PDF | HTML Oct 31, 2025
Application note MOSFET Support and Training Tools (Rev. G) PDF | HTML Oct 27, 2025
Application note Avoid Common Mistakes When Selecting And Designing With Power MOSFETs PDF | HTML Nov 6, 2024
Application note Semiconductor and IC Package Thermal Metrics (Rev. D) PDF | HTML Mar 25, 2024
Application note Using MOSFET Transient Thermal Impedance Curves In Your Design PDF | HTML Dec 18, 2023
Application note Solving Assembly Issues with Chip Scale Power MOSFETs PDF | HTML Dec 14, 2023
Application note Using MOSFET Safe Operating Area Curves in Your Design PDF | HTML Mar 13, 2023
Application brief Tips for Successfully Paralleling Power MOSFETs PDF | HTML May 31, 2022
Application note AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) Jun 14, 2019

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