Product details

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  • IEEE 802.3 Compliant, PCI V2.2 Media Access
    Controller (MAC) and Bus Interface Unit (BIU)
    Supports Traditional Data Rates of 10 Mb/s
    Ethernet and 100 Mb/s Fast Ethernet (Through
    Internal PHY)
  • Bus Master – Burst Sizes of up to 128 Dwords
    (512 Bytes)
  • BIU Compliant With PC 97 and PC 98 Hardware
    Design Guides, PC 99 Hardware Design Guide
    Draft, ACPI v1.0, PCI Power Management
    Specification v1.1, OnNow Device Class Power
    Management Reference Specification – Network
    Device Class v1.0a
  • Wake on LAN (WoL) Support Compliant With
    PC98, PC99, SecureOn, and OnNow, Including
    Directed Packets, Magic Packet™ VLAN Packets,
    ARP Packets, Pattern Match Packets, and PHY
    Status Change
  • Clkrun Function for PCI Mobile Design Guide
  • Virtual LAN (VLAN) and Long Frame Support
  • Support for IEEE 802.3× Full-Duplex Flow Control
  • Extremely Flexible Rx Packet Filtration Including:
    Single Address Perfect Filter With MSb Masking,
    Broadcast, 512 Entry Multicast and Unicast Hash
    Table, Deep Packet Pattern Matching for up to
    Four Unique Patterns
  • Statistics Gathered for Support of RFC 1213
    (MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3
    LME, Reducing CPU Overhead for Management
  • Internal 2KB Transmit and 2KB Receive Data
    FIFOs
  • Serial EEPROM Port With Auto-Load of
    Configuration Data From EEPROM at Power On
  • Flash or PROM Interface for Remote Boot Support
  • Fully Integrated IEEE 802.3 3.3-V CMOS Physical
    Layer
  • IEEE 802.3 10BASE-T Transceiver With Integrated
    Filters IEEE 802.3u 100BASE-TX Transceiver
  • Fully integrated ANSI X3.263 Compliant TP-PMD
    Physical Sublayer With Adaptive Equalization and
    Baseline Wander Compensation
  • IEEE 802.3u Auto-Negotiation – Advertised
    Features Configurable Through EEPROM
  • Full-Duplex Support for 10- and 100-Mb/s Data
    Rates
  • Single 25-MHz Reference Clock
  • 144-pin LQFP Package
  • Low-Power 3.3-V CMOS Design With Typical
    Consumption of 383 mW Operating, 297 mW
    During WoL, and 53 mW During Sleep Mode
  • IEEE 802.3u MII for Connecting Alternative
    External Physical Layer Devices
  • 3.3-V Signaling With 5-V Tolerant I/O
  • IEEE 802.3 Compliant, PCI V2.2 Media Access
    Controller (MAC) and Bus Interface Unit (BIU)
    Supports Traditional Data Rates of 10 Mb/s
    Ethernet and 100 Mb/s Fast Ethernet (Through
    Internal PHY)
  • Bus Master – Burst Sizes of up to 128 Dwords
    (512 Bytes)
  • BIU Compliant With PC 97 and PC 98 Hardware
    Design Guides, PC 99 Hardware Design Guide
    Draft, ACPI v1.0, PCI Power Management
    Specification v1.1, OnNow Device Class Power
    Management Reference Specification – Network
    Device Class v1.0a
  • Wake on LAN (WoL) Support Compliant With
    PC98, PC99, SecureOn, and OnNow, Including
    Directed Packets, Magic Packet™ VLAN Packets,
    ARP Packets, Pattern Match Packets, and PHY
    Status Change
  • Clkrun Function for PCI Mobile Design Guide
  • Virtual LAN (VLAN) and Long Frame Support
  • Support for IEEE 802.3× Full-Duplex Flow Control
  • Extremely Flexible Rx Packet Filtration Including:
    Single Address Perfect Filter With MSb Masking,
    Broadcast, 512 Entry Multicast and Unicast Hash
    Table, Deep Packet Pattern Matching for up to
    Four Unique Patterns
  • Statistics Gathered for Support of RFC 1213
    (MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3
    LME, Reducing CPU Overhead for Management
  • Internal 2KB Transmit and 2KB Receive Data
    FIFOs
  • Serial EEPROM Port With Auto-Load of
    Configuration Data From EEPROM at Power On
  • Flash or PROM Interface for Remote Boot Support
  • Fully Integrated IEEE 802.3 3.3-V CMOS Physical
    Layer
  • IEEE 802.3 10BASE-T Transceiver With Integrated
    Filters IEEE 802.3u 100BASE-TX Transceiver
  • Fully integrated ANSI X3.263 Compliant TP-PMD
    Physical Sublayer With Adaptive Equalization and
    Baseline Wander Compensation
  • IEEE 802.3u Auto-Negotiation – Advertised
    Features Configurable Through EEPROM
  • Full-Duplex Support for 10- and 100-Mb/s Data
    Rates
  • Single 25-MHz Reference Clock
  • 144-pin LQFP Package
  • Low-Power 3.3-V CMOS Design With Typical
    Consumption of 383 mW Operating, 297 mW
    During WoL, and 53 mW During Sleep Mode
  • IEEE 802.3u MII for Connecting Alternative
    External Physical Layer Devices
  • 3.3-V Signaling With 5-V Tolerant I/O

The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at low-cost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully implements the V2.2 33-MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe gap.

The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at low-cost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully implements the V2.2 33-MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe gap.

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Technical documentation

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Type Title Date
* Data sheet Integrated PCI Ethernet Media Access Contrlr & Phy Layer (MacPhyter-II) datasheet (Rev. E) 31 Dec 2015
User guide DP83816-MAAP User Guide 23 Feb 2012
Application note AN-1351 MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER 05 Jan 2005
Application note AN-1287 DP83815 MacPHYTER and DP83816 MacPHYTER-II High Data Rate Stress Testing 01 May 2004
Application note AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II 01 May 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Driver or library

DP83815-6MACPHYTER-SW — DP83816 MacPHYTER II software drivers & utilities

Ethernet drivers for the DP83815 and DP83816 media access controller and physical layer (MAC+PHY) devices.
Driver or library

ETHERNET-SW — Ethernet PHY Linux drivers & tools

The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.

The USB-2-MDIO software lets you directly access the registers during debug and (...)

Driver or library

DP83816 'MacPHYTER II' Software Drivers & Utilities

SLLC425.ZIP (1285 KB)
Driver or library

DP83816-MAAP Unix/Linux Driver

SNLC026.ZIP (100 KB)
Simulation model

DP83816 IBIS Model

SNLM002.ZIP (47 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
CAD/CAE symbol

DP83816 Orcad Sysmbols

SNLC041.ZIP (10 KB)
Package Pins Download
LQFP (PGE) 144 View options

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