Packaging information
| Package | Pins CFP (NBB) | 68 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 12 | JEDEC TRAY (5+1) |
Features for the LM98640QML-SP
- Radiation Hardened
- TID 100 krad(Si)
- Single Event Latch-Up (SEL) Immune to LET = 120 MeV-cm2/mg
- Single Event Functional Interrupt (SEFI) Free to 120 MeV-cm2/mg
- SMD 5962R1820301VXC
- ADC Resolution: 14-Bit
- ADC Sampling Rate: 5 MSPS to 40 MSPS
- Input Level: 2.85 V
- Supply Voltages 3.3 V and 1.8 V (Nominal)
- 125 mW per Channel at 15 MSPS
- 178 mW per Channel at 40 MSPS
- CDS or S/H Processing for CCD or CIS Sensors
- CDS or S/H Gain 0 dB or 6 dB
- Programmable Analog Gain for Each Channel
- 256 Steps; Range –3 dB to 18 dB
- Programmable Analog Offset Correction
- Fine and Coarse DAC Resolution ±8 Bits
- Fine DAC Range ±5 mV
- Coarse DAC Range ±250 mV
- Programmable Input Clamp Voltage
- Programmable Sample Edge: 1/64th Pixel Period
- INL at 15 MHz: ±3.5 LSB
- Noise Floor: –79 dB
- Crosstalk: –80 dB
- Operating Temp: –55°C to 125°C
Description for the LM98640QML-SP
The LM98640QML-SP is a fully integrated, high performance 14-Bit, 5-MSPS to 40-MSPS signal processing solution. The Serial LVDS output format performs well during single event exposure, preventing data loss. The LM98640QML-SP has an adaptive power scaling feature to optimize power consumption based on the operating frequency and amount of gain required. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for CIS and CMOS image sensors). The sampling edges are programmable to a resolution of 1/64th of a pixel period. Both the CDS and S/H have a programmable gain of either 0 dB or 6 dB. The signal paths utilize two ±8-bit offset correction DACs for coarse and fine offset correction, and 8-bit Programmable Gain Amplifiers (PGA) that can be programmed independently for each input. The signals are then routed to two on chip 14-bit 40-MHz high performance analog-to-digital converters (ADC). The fully differential processing channel provides exceptional noise immunity, having a very low noise floor of –79 dB at 1x gain.