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LMK02000

ACTIVE

1 to 800-MHz, precision clock distributor with integrated PLL and 3 LVDS / 5 LVPECL outputs

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Data sheet

LMK02000

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS Operating temperature range (°C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
Function Clock generator Number of outputs 8 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS Operating temperature range (°C) -40 to 85 Features Integrated integer-N PLL, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • 20 fs Additive Jitter
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • Clock Output Frequency Range of 1 to 800 MHz
  • 3 LVDS and 5 LVPECL Clock Outputs
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 20 fs Additive Jitter
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • Clock Output Frequency Range of 1 to 800 MHz
  • 3 LVDS and 5 LVPECL Clock Outputs
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioner comes in a 48-pin WQFN package and is footprint compatible with other clocking devices in the same family.

The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioner comes in a 48-pin WQFN package and is footprint compatible with other clocking devices in the same family.
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Technical documentation

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Type Title Date
* Data sheet LMK02000 Precision Clock Conditioner with Integrated PLL datasheet (Rev. D) 04 Sep 2007
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
EVM User's guide LMK02000 Evaluation Board User's Guide (Rev. A) 25 Nov 2013
More literature AN-1734 Using the LMK03000C to Clean Recovered Clocks (Rev. B) 26 Apr 2013
More literature AN-1821 CPRI Repeater System (Rev. A) 26 Apr 2013
More literature High Speed ADCs with Interfacing, Driving and Clocking Schemes (Rev. A) 26 Apr 2013
More literature Selecting Amplifiers, ADCs, and Clocks for High-Performance Signal Paths 13 Sep 2007
More literature Generating Precision Clocks for Time- Interleaved ADCs 02 Aug 2007
Design guide Clock Conditioner Owner's Manual 10 Nov 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Application software & framework

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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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IDE, configuration, compiler or debugger

CODELOADER — CodeLoader Software for device register programming

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

Which software do I use?

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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (RHS) 48 View options

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