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LMK03200

ACTIVE

Precision 0-delay clock conditioner with integrated VCO

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Data sheet

LMK03200

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.
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Technical documentation

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Type Title Date
* Data sheet LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO datasheet (Rev. C) 19 Apr 2013
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
EVM User's guide LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Eval 26 Jan 2012
Design guide Clock Conditioner Owner's Manual 10 Nov 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK03200EVAL — LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Evaluation Board

The LMK03200 Evaluation Board simplifies evaluation of the LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO. Configuring and controlling the board is accomplished using Texas Instruments' CodeLoader software, which can be downloaded from TI's website.

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Application software & framework

CLOCKDESIGNTOOL — Clock Design Tool - Loop Filter & Device Configuration + Simulation

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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IDE, configuration, compiler or debugger

CODELOADER — CodeLoader Software for device register programming

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (RHS) 48 View options
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