The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Part number | Order | Technology Family | VCC (Min) (V) | VCC (Max) (V) | Channels (#) | IOL (Max) (mA) | IOH (Max) (mA) | ICC (uA) | Input type | Output type | Features | Data rate (Mbps) | Rating | Operating temperature range (C) | Package Group |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SN74ABT125 |
|
ABT | 4.5 | 5.5 | 4 | 64 | -32 | 30000 | TTL-Compatible CMOS | 3-State |
Ultra high speed (tpd <5ns)
Partial power down (Ioff) Over-voltage tolerant inputs Power up 3-state |
300 | Catalog | -40 to 85 |
PDIP | 14
SOIC | 14 SO | 14 SSOP | 14 TSSOP | 14 VQFN | 14 |
| SN54ABT125 | Samples not available | ABT | 4.5 | 5.5 | 4 | 64 | -32 | 250 | TTL-Compatible CMOS | 3-State |
Ultra high speed (tpd <5ns)
Partial power down (Ioff) Over-voltage tolerant inputs Power up 3-state |
300 | Military | -55 to 125 |
CDIP | 14
CFP | 14 LCCC | 20 |
