SN74ABT125

ACTIVE

Quadruple Bus Buffer Gates With 3-State Outputs

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Product details

Parameters

Technology Family ABT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 4 IOL (Max) (mA) 64 ICC (Max) (uA) 30000 IOH (Max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs, Power up 3-state Data rate (Mbps) 300 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

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Description

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54ABT125, SN74ABT125 datasheet (Rev. I) Oct. 30, 2002
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application notes Quad Flatpack No-Lead Logic Packages (Rev. D) Feb. 16, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) Mar. 01, 1997
Application notes Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODELS Download
SCBM001C.ZIP (8 KB) - IBIS Model
SIMULATION MODELS Download
SCBM157.ZIP (7 KB) - PSpice Model
SIMULATION MODELS Download
SCEJ184.ZIP (118 KB) - HSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

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