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SN74AHC1G04

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Single Inverter Gate

Data sheet
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Single Inverter Gate

SN74AHC1G04

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family AHC VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 1 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Data rate (Mbps) 150 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 3 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 open-in-new Find other Inverting buffer/driver

Features

  • Operating Range 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 5 V
  • Schmitt-Trigger Action at All Inputs Makes the
    Circuit Tolerant for Slower Input Rise and Fall
    Time
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
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Description

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

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Technical documentation

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Type Title Date
* Datasheet SN74AHC1G04 Single Inverter Gate datasheet (Rev. T) Jan. 22, 2016
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODELS Download
SCLM003.ZIP (13 KB) - IBIS Model
SIMULATION MODELS Download
SCLM028.ZIP (6 KB) - IBIS Model
SIMULATION MODELS Download
SCLM029.ZIP (5 KB) - IBIS Model
SIMULATION MODELS Download
SCLM030.ZIP (6 KB) - IBIS Model
SIMULATION MODELS Download
SCLM031.ZIP (5 KB) - IBIS Model
SIMULATION MODELS Download
SCLM113.TSC (25 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SCLM114.ZIP (3 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SCLM274.ZIP (7 KB) - PSpice Model

Reference designs

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TIDA-01057 — This reference design is designed for high performance data acquisition(DAQ) systems to improve the dynamic range of 20 bit differential input ADCs. Many DAQ systems require the measurement capability at a wide FSR (Full Scale Range) in order to obtain sufficient signal dynamic range. Many earlier (...)
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20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI
TIDA-01056 — This reference design for high performance data acquisition (DAQ) systems optimizes power stage in order to reduce power consumption and minimize the effect of EMI from switching regulator by using LMS3635-Q1 buck converter.  This reference designs yields 7.2% efficiency improvement at most (...)
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20-bit, 1-MSPS Isolator Optimized Data Acquisition Reference Design Maximizing SNR and Sample Rate
TIDA-01037 — TIDA-01037 is a 20-bit, 1 MSPS isolated analog input data acquisition reference design that utilizes two different isolator devices to maximize signal chain SNR and sample rate performance. For signals requiring low jitter, such as ADC sampling clocks, TI’s ISO73xx family of low jitter devices (...)
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Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment
TIDA-01051 — The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as (...)
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Optimized Analog Front End DAQ System Reference Design for 18 bit SAR Data Converters
TIDA-01050 — The TIDA-01050 reference design aims to improve the integration, power consumption, performance, and clocking issues typically associated with automatic test equipment. This design is applicable to any ATE system but most applicable to systems requiring a large number of input channels.
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ADC Driver Reference Design Improving Full Scale THD Using Negative Supply
TIDA-01052 — The TIDA-01052 reference design aims to highlight system performance increases seen using a negative voltage rail on the analog front end driver amplifiers rather than ground. This concept is relative to all analog front ends, however this design is aimed specifically at automatic test equipment.
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options

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