Product details

Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
Technology Family AHC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 IOL (Max) (mA) 8 IOH (Max) (mA) -8 ICC (Max) (uA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs Rating Catalog
SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1
  • Operating Range 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 5 V
  • Schmitt-Trigger Action at All Inputs Makes the
    Circuit Tolerant for Slower Input Rise and Fall
    Time
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • Operating Range 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 5 V
  • Schmitt-Trigger Action at All Inputs Makes the
    Circuit Tolerant for Slower Input Rise and Fall
    Time
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

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Technical documentation

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Type Title Date
* Data sheet SN74AHC1G04 Single Inverter Gate datasheet (Rev. T) 22 Jan 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
In stock
Limit: 5
Simulation model

SN74AHC1G04 IBIS Model

SCLM003.ZIP (13 KB) - IBIS Model
Simulation model

SN74AHC1G04H IBIS Model

SCLM028.ZIP (6 KB) - IBIS Model
Simulation model

SN74AHC1G04H IBIS Model

SCLM029.ZIP (5 KB) - IBIS Model
Simulation model

SN74AHC1G04H IBIS Model

SCLM030.ZIP (6 KB) - IBIS Model
Simulation model

SN74AHC1G04H IBIS Model

SCLM031.ZIP (5 KB) - IBIS Model
Simulation model

SN74AHC1G04 TINA-TI Reference Design

SCLM113.TSC (25 KB) - TINA-TI Reference Design
Simulation model

SN74AHC1G04 TINA-TI Spice Model

SCLM114.ZIP (3 KB) - TINA-TI Spice Model
Simulation model

SN74AHC1G04 Behavioral SPICE Model

SCLM274.ZIP (7 KB) - PSpice Model
参考设计

TIDA-070005 — 3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-grade current sharing point-of-load (POL) reference design

This is a 24-A DC/DC space power hardware reference design.

As FPGA and ASIC technology advances, the core voltage requirements get lower but the current demand is larger. The newest space grade FPGAs and ASICS require low voltage and high currents for their core power consumption. These high current (...)

参考设计

TIDA-01434 — Isolated, Transformerless, Bipolar Supply for 24-Bit ADCs Reference Design

This isolated, 3.65-mm thin reference design enables highly-integrated, bipolar input and high-performance solutions with a 24-bit delta-sigma analog-to-digital converter (ADC). Modern analog input modules need high performance in different aspects such as higher channel density at the same room (...)
参考设计

TIDA-01054 — Multi-Rail Power Reference Design for Eliminating EMI Effects in High Performance DAQ Systems

The TIDA-01054 reference design helps eliminate the performance degrading effects of EMI on Data Acquisition (DAQ) systems greater than 16 bits with the help of the LM53635 buck converter. The buck converter enables the designer to place power solutions close to the signal path without the unwanted (...)
参考设计

TIDA-01055 — ADC Voltage Reference Buffer Optimization Reference Design for High Performance DAQ Systems

The TIDA-01055 reference design for high performance DAQ Systems optimizes the ADC reference buffer to improve SNR performance and reduce power consumption with the TI OPA837 high-speed op amp. This device is used in a composite buffer configuration and provides a 22% power improvement over (...)
参考设计

TIDA-01057 — Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC

This reference design is designed for high performance data acquisition(DAQ) systems to improve the dynamic range of 20 bit differential input ADCs. Many DAQ systems require the measurement capability at a wide FSR (Full Scale Range) in order to obtain sufficient signal dynamic range. Many earlier (...)
参考设计

TIDA-01056 — 20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI

This reference design for high performance data acquisition (DAQ) systems optimizes power stage in order to reduce power consumption and minimize the effect of EMI from switching regulator by using LMS3635-Q1 buck converter.  This reference designs yields 7.2% efficiency improvement at most (...)
参考设计

TIDA-01037 — 20-bit, 1-MSPS Isolator Optimized Data Acquisition Reference Design Maximizing SNR and Sample Rate

TIDA-01037 is a 20-bit, 1 MSPS isolated analog input data acquisition reference design that utilizes two different isolator devices to maximize signal chain SNR and sample rate performance. For signals requiring low jitter, such as ADC sampling clocks, TI’s ISO73xx family of low jitter devices (...)
参考设计

TIDA-01051 — Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as (...)
参考设计

TIDA-01050 — Optimized Analog Front End DAQ System Reference Design for 18 bit SAR Data Converters

The TIDA-01050 reference design aims to improve the integration, power consumption, performance, and clocking issues typically associated with automatic test equipment. This design is applicable to any ATE system but most applicable to systems requiring a large number of input channels.
参考设计

TIDA-01052 — ADC Driver Reference Design Improving Full Scale THD Using Negative Supply

The TIDA-01052 reference design aims to highlight system performance increases seen using a negative voltage rail on the analog front end driver amplifiers rather than ground. This concept is relative to all analog front ends, however this design is aimed specifically at automatic test equipment.
Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options

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