SN74AHC1G04

5 mm² 2.9 x 1.6

2 mm² 1.65 x 1.2

4 mm² 2 x 2.1

Operating Range 2 V to 5.5 V
Max t_pd of 6.5 ns at 5 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17

Operating Range 2 V to 5.5 V
Max t_pd of 6.5 ns at 5 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17

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The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74AHC1G04 Single Inverter Gate datasheet (Rev. T)	22 Jan 2016
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	More literature	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	More literature	Logic Cross-Reference (Rev. A)	07 Oct 2003
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)	02 Dec 2002
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)	24 Feb 2000
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	08 Sep 1999
	More literature	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)	01 Apr 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	Live Insertion	01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.

User guide

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Simulation model

SN74AHC1G04 IBIS Model

SCLM003.ZIP (13 KB) - IBIS Model

Simulation model

SN74AHC1G04H IBIS Model

SCLM028.ZIP (6 KB) - IBIS Model

Simulation model

SN74AHC1G04H IBIS Model

SCLM029.ZIP (5 KB) - IBIS Model

Simulation model

SN74AHC1G04H IBIS Model

SCLM030.ZIP (6 KB) - IBIS Model

Simulation model

SN74AHC1G04H IBIS Model

SCLM031.ZIP (5 KB) - IBIS Model

Simulation model

SN74AHC1G04 TINA-TI Reference Design

SCLM113.TSC (25 KB) - TINA-TI Reference Design

Simulation model

SN74AHC1G04 TINA-TI Spice Model

SCLM114.ZIP (3 KB) - TINA-TI Spice Model

Simulation model

SN74AHC1G04 Behavioral SPICE Model

SCLM274.ZIP (7 KB) - PSpice Model

参考设计

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TIDA-01052 — ADC Driver Reference Design Improving Full Scale THD Using Negative Supply

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