SN74ALS09

ACTIVE

4-ch, 2-input, 4.5-V to 5.5-V bipolar AND gates with open-collector outputs

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Product details

Parameters

Technology Family ALS Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) 0 Input type Bipolar Output type Open-Collector Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 75 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other AND gates

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other AND gates

Features

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

open-in-new Find other AND gates

Description

These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A \x95 B or in positive logic. The open-collector outputs require pullup resistors to perform correctly. These outputs may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOH levels.

 

The SN54ALS09 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS09 is characterized for operation from 0°C to 70°C.

 

 

open-in-new Find other AND gates
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Technical documentation

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Type Title Date
* Data sheet Quadruple 2-Input Positive-AND Gates With Open-Collector Outputs datasheet (Rev. B) Dec. 01, 1994
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDAM076.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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