Single 0.8-V to 3.6-V low power buffer with Schmitt-Trigger inputs
Product details
Parameters
Package | Pins | Size
Features
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Includes Schmitt-Trigger Inputs
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.1 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
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Description
The AUP family of devices is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN74AUP1G17 Low-Power Single Schmitt-Trigger Buffer datasheet (Rev. J) | Sep. 29, 2017 |
Application note | Debounce a Switch | Oct. 08, 2020 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | Jul. 06, 2018 | |
Application note | Designing and Manufacturing with TI's X2SON Packages | Aug. 23, 2017 | |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | How to Select Little Logic (Rev. A) | Jul. 26, 2016 | |
Application note | Understanding Schmitt Triggers | Sep. 21, 2011 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
Reference designs
Design files
-
download TIDA-00377 BOM.pdf (72KB) -
download TIDA-00377 Assembly Drawing.pdf (188KB) -
download TIDA-00377 PCB.pdf (1381KB) -
download TIDA-00377 CAD Files.zip (15480KB) -
download TIDA-00377 Gerber.zip (642KB)
Design files
-
download TIDA-00268 BOM.pdf (37KB) -
download TIDA-00268 Assembly Drawing.pdf (50KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
DSBGA (YFP) | 4 | View options |
DSBGA (YZP) | 5 | View options |
SC70 (DCK) | 5 | View options |
SON (DRY) | 6 | View options |
SON (DSF) | 6 | View options |
SOT-23 (DBV) | 5 | View options |
SOT-5X3 (DRL) | 5 | View options |
X2SON (DPW) | 5 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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