SN74AVC2T45-Q1

ACTIVE

Automotive Dual-Bit Dual-Supply Bus Transceiver with Config Voltage Translation and 3-State

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Automotive Dual-Bit Dual-Supply Bus Transceiver with Config Voltage Translation and 3-State

SN74AVC2T45-Q1

ACTIVE

Product details

Parameters

Technology Family AVC Applications GPIO, I2S Bits (#) 2 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Output voltage (Min) (V) 1.2 Output voltage (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Automotive open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

VSSOP (DCU) 8 6 mm² 2 x 3.1 open-in-new Find other Direction-controlled voltage translators

Features

  • Qualified for Automotive Applications
  • Control Inputs VIH/VIL Levels Are
    Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to
    Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates
    • 500 Mbps (1.8-V to 3.3-V Translation)
    • 320 Mbps (<1.8-V to 3.3-V Translation)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 17
Type Title Date
* Datasheet SN74AVC2T45-Q1 Dual-Bit Dual-Supply Bus Transceiver datasheet Jun. 30, 2010
Selection guide Voltage translation buying guide Jun. 13, 2019
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) Apr. 30, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. A) Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature LCD Module Interface Application Clip May 09, 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) Aug. 20, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) Jul. 07, 1999
Application note AVC Logic Family Technology and Applications (Rev. A) Aug. 26, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
20
Description

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

Features
  • SMB connector available for high speed operation
  • Ground port available on each header pin to maintain signal integrity
  • DIR and OE have 10K ohm pull up /pull down resistor options
  • Designed to support up to 20 different devices
EVALUATION BOARD Download
399
Description
The LMK04610EVM features LMK04610 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 900 mW with all outputs running, LMK04610 supports sub-74 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
Features
  • Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz  at 122.88 MHz output frequency
  • Integrated Loopfilter support easy prototyping
  • 0.9 W typical power consumption for 10 outputs at 122.88 MHz
  • Jumper configurable supplies with on-board LDOs and DCDC converters
  • GUI platform for full access (...)
EVALUATION BOARD Download
499
Description
The LMK04616EVM features LMK04616 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 1200 mW with 16 outputs running, LMK04616 supports 65 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
Features
  • Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
  • Integrated Loopfilter support easy prototyping
  • 1.2 W typical power consumption for 16 outputs at 122.88 MHz
  • Jumper configurable supplies with on-board LDOs and DCDC converters
  • GUI platform for full access (...)

CAD/CAE symbols

Package Pins Download
VSSOP (DCU) 8 View options

Ordering & quality

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