SN74CBT3253C

ACTIVE

5-V, 4:1, 2-channel FET bus switch with –2-V undershoot protection

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5-V, 4:1, 2-channel FET bus switch with –2-V undershoot protection

SN74CBT3253C

ACTIVE

Product details

Parameters

Configuration 4:1 Number of channels (#) 2 Ron (Typ) (Ohms) 3 Bandwidth (MHz) 200 Operating temperature range (C) -40 to 85 Features Powered-off protection, Supports I2C signals, Undershoot protection Input/output continuous current (Max) (mA) 128 Rating Catalog CON (Typ) (pF) 22 open-in-new Find other Analog switches/muxes

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 SSOP (DB) 16 48 mm² 6.2 x 7.8 SSOP (DBQ) 16 29 mm² 4.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 VQFN (RGY) 16 14 mm² 4 x 3.5 open-in-new Find other Analog switches/muxes

Features

  • SN74CBT3253C Functionally Identical to Industry-Standard ’3253 Function
  • Undershoot Protection for Off-Isolation on A and B Ports up to -2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 3 µA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports I2C Bus Expansion
  • Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating

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Description

The SN74CBT3253C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3253C provides protection for undershoot up to -2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3253C is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE, 2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE is low, the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74CBT3253C datasheet (Rev. B) Jan. 25, 2007
Application notes CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. A) Jun. 30, 2020
Application notes Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application notes Multiplexers and Signal Switches Glossary Mar. 06, 2020
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Application notes Eliminate power Sequencing with powered-off protection signal switches (Rev. B) Jan. 15, 2019
Technical articles Is charge injection causing output voltage errors in your industrial control system? Oct. 18, 2018
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003
Application notes CBT-C, CB3T, and CB3Q Signal-Switch Families Feb. 04, 2003

Design & development

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Hardware development

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The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


INTERFACE ADAPTERS Download
document-generic User guide
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Description
The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
Features
  • Quick testing of TI's surface mount packages 
  • Allows suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 16 most popular leadless packages with a single panel

Design tools & simulation

SIMULATION MODELS Download
SCDM034.ZIP (26 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
SSOP (DB) 16 View options
SSOP (DBQ) 16 View options
TSSOP (PW) 16 View options
VQFN (RGY) 16 View options

Ordering & quality

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