Switch Connection Between Two PortsThe SN74CBTLV3861 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device is organized as one 10-bit bus switch. When output enable (OE\) is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74CBTLV3861 datasheet (Rev. H) | Oct 10, 2003 | |
| Application note | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | Jun 2, 2022 | |
| Application note | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | Dec 1, 2021 | |
| Application brief | Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) | PDF | HTML | Jan 6, 2021 |
For additional terms or required resources, click any title below to view the detail page where available.
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TVSOP (DGV) | 24 | Ultra Librarian |
| SOIC (DW) | 24 | Ultra Librarian |
| SOP (NS) | 24 | Ultra Librarian |
| TSSOP (PW) | 24 | Ultra Librarian |
| SSOP (DBQ) | 24 | Ultra Librarian |
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