SN74LV08A-Q1

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Product details

Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 70 Rating Automotive Operating temperature range (C) -40 to 105
Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (Max) (Mbps) 70 Rating Automotive Operating temperature range (C) -40 to 105
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV08A performs the Boolean function Y = A • B or Y = (A\ + B\) in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV08A performs the Boolean function Y = A • B or Y = (A\ + B\) in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet Quadruple 2-Input Positive-AND Gate datasheet (Rev. C) 29 Jan 2008
More literature Automotive Logic Devices Brochure 27 Aug 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Limit: 5
Simulation model

SN74LV08A Behavioral SPICE Model

SCLM190.ZIP (7 KB) - PSpice Model
Package Pins Download
TSSOP (PW) 14 View options

Ordering & quality

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