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SN74LVC1G3208

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Single 3-Input Positive OR-AND Gate

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Data sheet

SN74LVC1G3208

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm)
  • Available in the Texas Instruments NanoStar and NanoFree Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 5 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.3 V)
  • Can Be Used in Three Combinations:
    • OR-AND Gate
    • OR Gate
    • AND Gate
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar and NanoFree Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 5 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.3 V)
  • Can Be Used in Three Combinations:
    • OR-AND Gate
    • OR Gate
    • AND Gate
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This device is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic.

By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C).

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This device is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic.

By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C).

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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* Data sheet SN74LVC1G3208 datasheet (Rev. B) Nov 24, 2013

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Supported products & hardware
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Simulation model

SN74LVC1G3208 IBIS Model (Rev. A)

SCEM474 (239 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
DSBGA (YZP) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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