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SN74LVC1G99

ACTIVE

Ultra-Configurable Multi-Function Gate With 3-State Outputs

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Data sheet

SN74LVC1G99

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² (— mm × — mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm)
  • Available in Texas Instruments
    NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Offers Nine Different Logic Functions in a Single Package
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows for Slow Input Transition Time and Better Noise Immunity at Input
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in Texas Instruments
    NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Offers Nine Different Logic Functions in a Single Package
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows for Slow Input Transition Time and Better Noise Immunity at Input
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LVC1G99 device is operational from 1.65 V to 5.5 V.

The SN74LVC1G99 device features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technologies are a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC1G99 device is operational from 1.65 V to 5.5 V.

The SN74LVC1G99 device features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technologies are a major breakthrough in IC packaging concepts, using the die as the package.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet Ultra-Configurable Multiple-Function Gate With 3-State Output datasheet (Rev. G) Nov 22, 2013
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application brief Utilizing Configurable Logic in System Design PDF | HTML Oct 30, 2024

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Simulation model

SN74LVC1G99 IBIS Model (Rev. A)

SCEM466 (276 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZP) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
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