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SN74LVC2G08

ACTIVE

2-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

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Data sheet

SN74LVC2G08

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in the Texas Instruments
    NanoStar™ and NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate
    Inputs From a Maximum of 5.5 V Down to the VCC
    Level
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoStar™ and NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate
    Inputs From a Maximum of 5.5 V Down to the VCC
    Level
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G08 device performs the Boolean function A × B or Y = A\ + B\ in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G08 device performs the Boolean function A × B or Y = A\ + B\ in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.
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SN74AUP2G08 ACTIVE 2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G126 ACTIVE 2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
Similar functionality to the compared device.
SN74AUP2G241 ACTIVE 2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G32 ACTIVE 2-ch, 2-input 0.8-V to 3.6-V low-power (< 1uA) OR gate Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G00 ACTIVE 2-ch, 2-input, 0.8-V to 3.6-V low power NAND gates Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G02 ACTIVE 2-ch, 2-input, 0.8-V to 3.6-V low power NOR gates Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AHC08 ACTIVE 4-ch, 2-input 2-V to 5.5-V high-speed (9 ns) AND gate Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA
SN74AUP2G125 ACTIVE 2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC2G08 Dual 2-Input Positive-AND Gate datasheet (Rev. N) PDF | HTML Dec 31, 2015
Application brief Simplifying Solid-State Relay Designs With Logic PDF | HTML Jan 8, 2021

Design & development

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Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
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Simulation model

HSPICE MODEL OF SN74LVC2G08

SCEJ207.ZIP (90 KB) - HSpice model
Supported products & hardware
Simulation model

SN74LVC2G08 Behavioral SPICE Model

SCEM620.ZIP (7 KB) - PSpice model
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SN74LVC2G08 IBIS Model (Rev. A)

SCEM285 (242 KB) - IBIS model
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